From patchwork Fri Dec 8 11:32:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 121152 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp539443qgn; Fri, 8 Dec 2017 03:33:27 -0800 (PST) X-Google-Smtp-Source: AGs4zMYyAHarqJ94F/43OGpLc6aPOA0kyhD7zAg92J/cdILCNTwetpD/Var5CkZ2j91f2yUXChpN X-Received: by 10.101.101.216 with SMTP id y24mr30468263pgv.236.1512732807129; Fri, 08 Dec 2017 03:33:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512732807; cv=none; d=google.com; s=arc-20160816; b=VNxbwxRyxuFizW9vucaPKjfxCrcDmpzIARdIFpPQ6bsOSmGRbeH/lyanAT8PwJxA5r zFZeKRs2AN3WLAXLRKEklkeA3md49jTUmkzDjndxkyUWTzdWVjLymnUnRdH2M1YAXP0S mMpQFsARCWMYd+w/4CjCglwm/OCM/8quv0nL9n3BKxR7IduQhI9DtbSznH8bRMVONJ42 ekKMhfjo7X/SAVO0fI351FbkGT6D6/IqdtUhlKjxhtbKCAxNptyP7d17ZJUvMpws4gML MEHJ1/q6JiCEgC/KMhdYMVqTgKXJ+fPvL16tQ6SvQTd52MjSA31LgXNE5czDwwbR5OUP uPuw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=TmtVdi2T4WwFbZ3b2QBUkVTUI5jl3HN+NkMxmfmBN+o=; b=sKZm9pfhB+h3nM3y1l/M76biPNjJ7fAUHeUwj+MDg7ayYQGcBzRpTjVSkT/Q9RbJlf 7j4wJekl94O5n6SpivXsoD2wy16lmYg7vjEOl4hEUAk8Gtpqr5O0XbRviEKKbaRbUTKc z4qsAKN8pCXXffyAmr9aYCVl1MmiFKuzUYVa5OqJ55YlAH7EYlqWxizi0aMjMVKn55sf tQ6fvjwWA6xdvHdkZwBGFkqVpNV6ibneEHSlympQbatCZ6p9Qis6ALbCKeTBVkNzRLru er89JBtgDbJ1gW++mGGUBhNFu3+5wObrUPH8yuPzl5cwOGF+QJklR/OoM2JQN3GqpdfM EDHg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gmUiiUeH; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v11si5387943plg.3.2017.12.08.03.33.26; Fri, 08 Dec 2017 03:33:27 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gmUiiUeH; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753550AbdLHLdW (ORCPT + 11 others); Fri, 8 Dec 2017 06:33:22 -0500 Received: from mail-wr0-f195.google.com ([209.85.128.195]:34308 "EHLO mail-wr0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753414AbdLHLdM (ORCPT ); Fri, 8 Dec 2017 06:33:12 -0500 Received: by mail-wr0-f195.google.com with SMTP id y21so10535896wrc.1 for ; Fri, 08 Dec 2017 03:33:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TmtVdi2T4WwFbZ3b2QBUkVTUI5jl3HN+NkMxmfmBN+o=; b=gmUiiUeHGlqBippk7MhztImH39/I5Ji+9CcLwJ2uWIeGBOEqoNG6Bu/VtJIiQkpG75 jgRkfKNaDr/FW5q0pQaAS50hVW00f4KhvBMc3wYv+Ke/b6TphmQGGukHLGovxjKtOEfu f8hXipOYqljtnY4ZMs+9HSQzsyn8YD2t93/0E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TmtVdi2T4WwFbZ3b2QBUkVTUI5jl3HN+NkMxmfmBN+o=; b=ngLxkCKPCpF+h4cvkSHG2r+V0WaL9J4KRuhYkuGMUILMy2ofEfsvvOG9B+7tjBQZJF FxR1J8OYJtaHH2aISJ/WtRXVIFc6dJPEf3F34n3+8M9ikQ62Ewwi+kakleu+QOR2wpES WSNYli6Ut8ILe4B8z8PCtoZ4BV2Dge8p09CVb+vI0Lmnh2Cp5H8fTK2qEaGA5lKm4bJC VtRTdnIDA0Lm7CF9OvNEV4MIdMphYjNCLwIxxFn6g7BmAlpwaAW2wvvrW/V1aRIzG4sB HU9FpQPXcVUdCTmlsb+RpvR0nb+eF3lVEqFiCe+vfqWMA/8uQz0fCIIoIsT1HDFWzGp+ W5hw== X-Gm-Message-State: AJaThX7nysee5JknLZSZyrqCTcO9yXhtRGUibgXgVUUpghNAYbc17IGO wbtRb6k4FiHkHYF3Ew36aU9pvw== X-Received: by 10.223.155.131 with SMTP id d3mr28783951wrc.29.1512732791395; Fri, 08 Dec 2017 03:33:11 -0800 (PST) Received: from lmecxl0911.lme.st.com ([80.215.241.46]) by smtp.gmail.com with ESMTPSA id x52sm9184518wrb.25.2017.12.08.03.33.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Dec 2017 03:33:10 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, daniel.lezcano@linaro.org, tglx@linutronix.de, arnd@arndb.de Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Benjamin Gaignard , Benjamin Gaignard Subject: [PATCH v9 4/6] clocksource: stm32: add clocksource support Date: Fri, 8 Dec 2017 12:32:48 +0100 Message-Id: <20171208113250.359-5-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171208113250.359-1-benjamin.gaignard@st.com> References: <20171208113250.359-1-benjamin.gaignard@st.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The stm32 timer hardware is currently only used as a clock event device, but it can be utilized as a clocksource as well. Implement this by enabling the free running counter in the hardware block and converting the clock event part from a count down event timer to a comparator based timer. Signed-off-by: Benjamin Gaignard --- drivers/clocksource/timer-stm32.c | 116 +++++++++++++++++++++++++++++--------- 1 file changed, 88 insertions(+), 28 deletions(-) -- 2.15.0 diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index 707808d91bf0..c9aed2314194 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -16,6 +16,8 @@ #include #include #include +#include +#include #include "timer-of.h" @@ -23,16 +25,16 @@ #define TIM_DIER 0x0c #define TIM_SR 0x10 #define TIM_EGR 0x14 +#define TIM_CNT 0x24 #define TIM_PSC 0x28 #define TIM_ARR 0x2c +#define TIM_CCR1 0x34 #define TIM_CR1_CEN BIT(0) -#define TIM_CR1_OPM BIT(3) +#define TIM_CR1_UDIS BIT(1) #define TIM_CR1_ARPE BIT(7) -#define TIM_DIER_UIE BIT(0) - -#define TIM_SR_UIF BIT(0) +#define TIM_DIER_CC1IE BIT(1) #define TIM_EGR_UG BIT(0) @@ -46,28 +48,44 @@ static int stm32_clock_event_shutdown(struct clock_event_device *evt) { struct timer_of *to = to_timer_of(evt); - writel_relaxed(0, timer_of_base(to) + TIM_CR1); + writel_relaxed(0, timer_of_base(to) + TIM_DIER); + return 0; } -static int stm32_clock_event_set_periodic(struct clock_event_device *evt) +static int stm32_clock_event_set_next_event(unsigned long evt, + struct clock_event_device *clkevt) { - struct timer_of *to = to_timer_of(evt); + struct timer_of *to = to_timer_of(clkevt); + unsigned long now, next; - writel_relaxed(timer_of_period(to), timer_of_base(to) + TIM_ARR); - writel_relaxed(TIM_CR1_ARPE | TIM_CR1_CEN, timer_of_base(to) + TIM_CR1); + next = readl_relaxed(timer_of_base(to) + TIM_CNT) + evt; + writel_relaxed(next, timer_of_base(to) + TIM_CCR1); + now = readl_relaxed(timer_of_base(to) + TIM_CNT); + + if ((next - now) > evt) + return -ETIME; + + writel_relaxed(TIM_DIER_CC1IE, timer_of_base(to) + TIM_DIER); return 0; } -static int stm32_clock_event_set_next_event(unsigned long evt, - struct clock_event_device *clkevt) +static int stm32_clock_event_set_periodic(struct clock_event_device *evt) { - struct timer_of *to = to_timer_of(clkevt); + struct timer_of *to = to_timer_of(evt); - writel_relaxed(evt, timer_of_base(to) + TIM_ARR); - writel_relaxed(TIM_CR1_ARPE | TIM_CR1_OPM | TIM_CR1_CEN, - timer_of_base(to) + TIM_CR1); + return stm32_clock_event_set_next_event(timer_of_period(to), evt); +} + +static int stm32_clock_event_set_oneshot(struct clock_event_device *evt) +{ + struct timer_of *to = to_timer_of(evt); + unsigned long val; + + val = readl_relaxed(timer_of_base(to) + TIM_CNT); + writel_relaxed(val, timer_of_base(to) + TIM_CCR1); + writel_relaxed(TIM_DIER_CC1IE, timer_of_base(to) + TIM_DIER); return 0; } @@ -79,6 +97,11 @@ static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id) writel_relaxed(0, timer_of_base(to) + TIM_SR); + if (clockevent_state_periodic(evt)) + stm32_clock_event_set_periodic(evt); + else + stm32_clock_event_shutdown(evt); + evt->event_handler(evt); return IRQ_HANDLED; @@ -89,7 +112,48 @@ static bool stm32_timer_is_32bits(struct timer_of *to) return readl_relaxed(timer_of_base(to) + TIM_ARR) == ~0UL; } -static int __init stm32_clockevent_init(struct device_node *node) +static void __init stm32_clockevent_init(struct timer_of *to) +{ + writel_relaxed(0, timer_of_base(to) + TIM_DIER); + writel_relaxed(0, timer_of_base(to) + TIM_SR); + + clockevents_config_and_register(&to->clkevt, + timer_of_rate(to), MIN_DELTA, ~0U); +} + +static void __iomem *stm32_timer_cnt __read_mostly; + +static u64 notrace stm32_read_sched_clock(void) +{ + return readl_relaxed(stm32_timer_cnt); +} + +static int __init stm32_clocksource_init(struct timer_of *to) +{ + writel_relaxed(~0U, timer_of_base(to) + TIM_ARR); + writel_relaxed(0, timer_of_base(to) + TIM_PSC); + writel_relaxed(0, timer_of_base(to) + TIM_SR); + writel_relaxed(0, timer_of_base(to) + TIM_DIER); + writel_relaxed(0, timer_of_base(to) + TIM_SR); + writel_relaxed(TIM_CR1_ARPE | TIM_CR1_UDIS, + timer_of_base(to) + TIM_CR1); + + /* Make sure that registers are updated */ + writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR); + + /* Enable controller */ + writel_relaxed(TIM_CR1_ARPE | TIM_CR1_UDIS | TIM_CR1_CEN, + timer_of_base(to) + TIM_CR1); + + stm32_timer_cnt = timer_of_base(to) + TIM_CNT; + sched_clock_register(stm32_read_sched_clock, 32, timer_of_rate(to)); + + return clocksource_mmio_init(stm32_timer_cnt, "stm32_timer", + timer_of_rate(to), 250, 32, + clocksource_mmio_readl_up); +} + +static int __init stm32_timer_init(struct device_node *node) { struct reset_control *rstc; struct timer_of *to; @@ -100,12 +164,13 @@ static int __init stm32_clockevent_init(struct device_node *node) return -ENOMEM; to->flags = TIMER_OF_IRQ | TIMER_OF_CLOCK | TIMER_OF_BASE; + to->clkevt.name = "stm32_clockevent"; to->clkevt.rating = 200; - to->clkevt.features = CLOCK_EVT_FEAT_PERIODIC; + to->clkevt.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC; to->clkevt.set_state_shutdown = stm32_clock_event_shutdown; to->clkevt.set_state_periodic = stm32_clock_event_set_periodic; - to->clkevt.set_state_oneshot = stm32_clock_event_shutdown; + to->clkevt.set_state_oneshot = stm32_clock_event_set_oneshot; to->clkevt.tick_resume = stm32_clock_event_shutdown; to->clkevt.set_next_event = stm32_clock_event_set_next_event; @@ -128,16 +193,11 @@ static int __init stm32_clockevent_init(struct device_node *node) goto deinit; } - writel_relaxed(0, timer_of_base(to) + TIM_ARR); - - writel_relaxed(0, timer_of_base(to) + TIM_PSC); - writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR); - writel_relaxed(TIM_DIER_UIE, timer_of_base(to) + TIM_DIER); - writel_relaxed(0, timer_of_base(to) + TIM_SR); + ret = stm32_clocksource_init(to); + if (ret) + goto deinit; - clockevents_config_and_register(&to->clkevt, - timer_of_period(to), - MIN_DELTA, ~0U); + stm32_clockevent_init(to); return 0; @@ -148,4 +208,4 @@ static int __init stm32_clockevent_init(struct device_node *node) return ret; } -TIMER_OF_DECLARE(stm32, "st,stm32-timer", stm32_clockevent_init); +TIMER_OF_DECLARE(stm32, "st,stm32-timer", stm32_timer_init);