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[209.132.180.67]) by mx.google.com with ESMTP id c7si3886914plr.486.2017.12.07.06.29.53; Thu, 07 Dec 2017 06:29:53 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=mQWhOn9E; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754087AbdLGO3w (ORCPT + 22 others); Thu, 7 Dec 2017 09:29:52 -0500 Received: from mail-wm0-f66.google.com ([74.125.82.66]:35508 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753762AbdLGO1W (ORCPT ); Thu, 7 Dec 2017 09:27:22 -0500 Received: by mail-wm0-f66.google.com with SMTP id f9so13332938wmh.0 for ; Thu, 07 Dec 2017 06:27:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JeYslYrYs80IFg4iNX1KkL4etF5OASMU6dHxAErRtHY=; b=mQWhOn9ENHevACRJOn4KwDhVq9lzjJCrY6QMn+jnsQNH2EhDCGzXmWw9pkWhdpiH/G 1/tkmhPvYyMZ/txdVJj+WtSPaEy/wmFjGYKoJhp7DXUadnY0Uyn0AAXyUTJWGjil0xR5 MSOi71EnHL/oYiCkvt7gC/OYBiqYnhQu9kJ7pTC6elVQMgvEOhER13hQgN+cS6kcWQto vXGlznqVswmtVKlWiDKBP1Bzd6UhLdcV+zZAc+MVPW5HgiH4shkpg2HjupBIXNexSakF +qnSepwoBnGEJ4h/cxI5OmAOe3sHKhlBg+5B5OXVX+vWiHh/4CJwhoUUAMLTPiDKC3rp sfsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JeYslYrYs80IFg4iNX1KkL4etF5OASMU6dHxAErRtHY=; b=PNAGaktxVxBa2Gbh+vQ6MMO8rP83JuRjdY3zrTsGhAMWzndD/R5ICzQimzmlnFHz+R 6sCb55NFysFw+2x9pb3Kk4ugYZF1HH9ike6oSnAyOO7JRKDK6xkkKcIuoHmlUnocEWFK xZx16bA0TgdOPkc/Yc/3I3INGejWM/eA94gYAowfpl65bhNJbuWj3VXZkRu9tA0gLVgf 6ZhkKFdD7hH/iZUCCzA2bV3aChG5NpvhgdNZ173As85o1wy6x+nMecrabyECtdMWYe/z 7BkXWLT51ExonsOioYZ5j0OUbe4yb1KqqmCPPMfiT+9LSzHC6zpd7zNIQ8SYX1u8AdSo v4Qw== X-Gm-Message-State: AKGB3mIHFYoJp/0hALwYGkxXdYm0qCVmXb2uW+/pFeGhR8homXN27MIZ 3JM1k68fHVZWy3GA54qMtxGiBQ== X-Received: by 10.28.128.214 with SMTP id b205mr1440776wmd.82.1512656841279; Thu, 07 Dec 2017 06:27:21 -0800 (PST) Received: from boomer.baylibre.local ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id t138sm6264520wme.16.2017.12.07.06.27.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Dec 2017 06:27:20 -0800 (PST) From: Jerome Brunet To: Andrew Lunn , Florian Fainelli Cc: Jerome Brunet , Kevin Hilman , netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next v2 3/8] net: phy: meson-gxl: add read and write helpers for bank registers Date: Thu, 7 Dec 2017 15:27:10 +0100 Message-Id: <20171207142715.32578-4-jbrunet@baylibre.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20171207142715.32578-1-jbrunet@baylibre.com> References: <20171207142715.32578-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add read and write helpers to manipulate banked registers on this PHY This helps clarify the settings applied to these registers in the init function and upcoming changes. Signed-off-by: Jerome Brunet --- drivers/net/phy/meson-gxl.c | 103 ++++++++++++++++++++++++++++---------------- 1 file changed, 67 insertions(+), 36 deletions(-) -- 2.14.3 diff --git a/drivers/net/phy/meson-gxl.c b/drivers/net/phy/meson-gxl.c index d82aa8cea401..05054770aefb 100644 --- a/drivers/net/phy/meson-gxl.c +++ b/drivers/net/phy/meson-gxl.c @@ -45,11 +45,13 @@ #define FR_PLL_DIV0 0x1c #define FR_PLL_DIV1 0x1d -static int meson_gxl_config_init(struct phy_device *phydev) +static int meson_gxl_open_banks(struct phy_device *phydev) { int ret; - /* Enable Analog and DSP register Bank access by */ + /* Enable Analog and DSP register Bank access by + * toggling TSTCNTL_TEST_MODE bit in the TSTCNTL register + */ ret = phy_write(phydev, TSTCNTL, 0); if (ret) return ret; @@ -59,55 +61,84 @@ static int meson_gxl_config_init(struct phy_device *phydev) ret = phy_write(phydev, TSTCNTL, 0); if (ret) return ret; - ret = phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE); - if (ret) - return ret; + return phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE); +} - /* Write CONFIG_A6*/ - ret = phy_write(phydev, TSTWRITE, 0x8e0d) +static void meson_gxl_close_banks(struct phy_device *phydev) +{ + phy_write(phydev, TSTCNTL, 0); +} + +static int meson_gxl_read_reg(struct phy_device *phydev, + unsigned int bank, unsigned int reg) +{ + int ret; + + ret = meson_gxl_open_banks(phydev); if (ret) - return ret; - ret = phy_write(phydev, TSTCNTL, - TSTCNTL_WRITE - | FIELD_PREP(TSTCNTL_REG_BANK_SEL, BANK_ANALOG_DSP) - | TSTCNTL_TEST_MODE - | FIELD_PREP(TSTCNTL_WRITE_ADDRESS, A6_CONFIG_REG)); + goto out; + + ret = phy_write(phydev, TSTCNTL, TSTCNTL_READ | + FIELD_PREP(TSTCNTL_REG_BANK_SEL, bank) | + TSTCNTL_TEST_MODE | + FIELD_PREP(TSTCNTL_READ_ADDRESS, reg)); if (ret) - return ret; + goto out; - /* Enable fractional PLL */ - ret = phy_write(phydev, TSTWRITE, 0x0005); + ret = phy_read(phydev, TSTREAD1); +out: + /* Close the bank access on our way out */ + meson_gxl_close_banks(phydev); + return ret; +} + +static int meson_gxl_write_reg(struct phy_device *phydev, + unsigned int bank, unsigned int reg, + uint16_t value) +{ + int ret; + + ret = meson_gxl_open_banks(phydev); if (ret) - return ret; - ret = phy_write(phydev, TSTCNTL, - TSTCNTL_WRITE - | FIELD_PREP(TSTCNTL_REG_BANK_SEL, BANK_BIST) - | TSTCNTL_TEST_MODE - | FIELD_PREP(TSTCNTL_WRITE_ADDRESS, FR_PLL_CONTROL)); + goto out; + + ret = phy_write(phydev, TSTWRITE, value); if (ret) - return ret; + goto out; - /* Program fraction FR_PLL_DIV1 */ - ret = phy_write(phydev, TSTWRITE, 0x029a); + ret = phy_write(phydev, TSTCNTL, TSTCNTL_WRITE | + FIELD_PREP(TSTCNTL_REG_BANK_SEL, bank) | + TSTCNTL_TEST_MODE | + FIELD_PREP(TSTCNTL_WRITE_ADDRESS, reg)); + +out: + /* Close the bank access on our way out */ + meson_gxl_close_banks(phydev); + return ret; +} + +static int meson_gxl_config_init(struct phy_device *phydev) +{ + int ret; + + /* Write CONFIG_A6*/ + ret = meson_gxl_write_reg(phydev, BANK_ANALOG_DSP, A6_CONFIG_REG, + 0x8e0d); if (ret) return ret; - ret = phy_write(phydev, TSTCNTL, - TSTCNTL_WRITE - | FIELD_PREP(TSTCNTL_REG_BANK_SEL, BANK_BIST) - | TSTCNTL_TEST_MODE - | FIELD_PREP(TSTCNTL_WRITE_ADDRESS, FR_PLL_DIV1)); + + /* Enable fractional PLL */ + ret = meson_gxl_write_reg(phydev, BANK_BIST, FR_PLL_CONTROL, 0x5); if (ret) return ret; /* Program fraction FR_PLL_DIV1 */ - ret = phy_write(phydev, TSTWRITE, 0xaaaa); + ret = meson_gxl_write_reg(phydev, BANK_BIST, FR_PLL_DIV1, 0x029a); if (ret) return ret; - ret = phy_write(phydev, TSTCNTL, - TSTCNTL_WRITE - | FIELD_PREP(TSTCNTL_REG_BANK_SEL, BANK_BIST) - | TSTCNTL_TEST_MODE - | FIELD_PREP(TSTCNTL_WRITE_ADDRESS, FR_PLL_DIV0)); + + /* Program fraction FR_PLL_DIV1 */ + ret = meson_gxl_write_reg(phydev, BANK_BIST, FR_PLL_DIV0, 0xaaaa); if (ret) return ret;