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[209.132.180.67]) by mx.google.com with ESMTP id 26si4141119pfo.269.2017.12.07.06.29.03; Thu, 07 Dec 2017 06:29:03 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=CC1xboEa; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753839AbdLGO1Y (ORCPT + 22 others); Thu, 7 Dec 2017 09:27:24 -0500 Received: from mail-wr0-f196.google.com ([209.85.128.196]:45782 "EHLO mail-wr0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753559AbdLGO1U (ORCPT ); Thu, 7 Dec 2017 09:27:20 -0500 Received: by mail-wr0-f196.google.com with SMTP id h1so7653182wre.12 for ; Thu, 07 Dec 2017 06:27:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bAipUEvgvM1Uc5xrra8bjleth2WsfGM5KkNvI1jPf0A=; b=CC1xboEa/+yuNu3DUMFgtZfwKG6mvHhsf3tEyJba5w+ZjHX6MzkdHF0RDe9SYpbAfe ZDlB2KCb2pidhmUjB7og10UsxiIz/OLR6VbfuZPxaSZhYg7JCXMaEQJAP3FWxxr6y/3z bTDXN9hEopJz/x6DvUJTCCzYHVU7evOyAfRuaIp6d66eDWTlPJ3Nf9cezbzJiJo7QR1u z8KU+oDfPvMEXUXE7AE3M0Ih+PdqOPObZx7BTelnnZQDEMrQxKN+HgoDG735o7ahkX8o dQ3Qv6d0SuATBMKpPNouO+YwNxYdu7LAiW/ENg/qf2oYbzFnpN34vUhwQvajludqpk7T tKNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bAipUEvgvM1Uc5xrra8bjleth2WsfGM5KkNvI1jPf0A=; b=tDuLfFZHc83jyHBWXTulk5JXbk002At+KXuSuGF3XDNQCAk4DAJwgFDP5kiX30JNZK 4WLDZyw8ALaIceIOi+oGAxprqmND3S6FsnOv+ZO9shWCOHUHU4wG6btAhUs3+mUv454u iTAEUH2mQ0f6IrPqP6UT4bI7cCVfNn2OuUjFWSAxViDwS1gty0mVkG1rRsgAqt+xdexb IKgmE6ZxjkLA4CAk10DNRSojwx8/xqqVTykftLMeFW2pXoeOyYTkxeFTCTSv2H6wx9tY H953XKls5sP42VjhJACOW3rDURCDCJj87lqDOzG8Dc9tLaGwYzSZwd8hNB1dzG5i8win E5vw== X-Gm-Message-State: AJaThX598FVe8BTTniywIbdUtOBuikARaNZKA2Nk2WH81nAx+5vdqiS1 YlQcO4Ccm9fhXSZYM7tH6bJOkg== X-Received: by 10.223.195.22 with SMTP id n22mr25876908wrf.212.1512656839229; Thu, 07 Dec 2017 06:27:19 -0800 (PST) Received: from boomer.baylibre.local ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id t138sm6264520wme.16.2017.12.07.06.27.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Dec 2017 06:27:18 -0800 (PST) From: Jerome Brunet To: Andrew Lunn , Florian Fainelli Cc: Jerome Brunet , Kevin Hilman , netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next v2 1/8] net: phy: meson-gxl: check phy_write return value Date: Thu, 7 Dec 2017 15:27:08 +0100 Message-Id: <20171207142715.32578-2-jbrunet@baylibre.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20171207142715.32578-1-jbrunet@baylibre.com> References: <20171207142715.32578-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Always check phy_write return values. Better to be safe than sorry Signed-off-by: Jerome Brunet --- drivers/net/phy/meson-gxl.c | 50 ++++++++++++++++++++++++++++++++++----------- 1 file changed, 38 insertions(+), 12 deletions(-) -- 2.14.3 Reviewed-by: Andrew Lunn diff --git a/drivers/net/phy/meson-gxl.c b/drivers/net/phy/meson-gxl.c index 1ea69b7585d9..7ddb709f69fc 100644 --- a/drivers/net/phy/meson-gxl.c +++ b/drivers/net/phy/meson-gxl.c @@ -25,27 +25,53 @@ static int meson_gxl_config_init(struct phy_device *phydev) { + int ret; + /* Enable Analog and DSP register Bank access by */ - phy_write(phydev, 0x14, 0x0000); - phy_write(phydev, 0x14, 0x0400); - phy_write(phydev, 0x14, 0x0000); - phy_write(phydev, 0x14, 0x0400); + ret = phy_write(phydev, 0x14, 0x0000); + if (ret) + return ret; + ret = phy_write(phydev, 0x14, 0x0400); + if (ret) + return ret; + ret = phy_write(phydev, 0x14, 0x0000); + if (ret) + return ret; + ret = phy_write(phydev, 0x14, 0x0400); + if (ret) + return ret; /* Write Analog register 23 */ - phy_write(phydev, 0x17, 0x8E0D); - phy_write(phydev, 0x14, 0x4417); + ret = phy_write(phydev, 0x17, 0x8E0D); + if (ret) + return ret; + ret = phy_write(phydev, 0x14, 0x4417); + if (ret) + return ret; /* Enable fractional PLL */ - phy_write(phydev, 0x17, 0x0005); - phy_write(phydev, 0x14, 0x5C1B); + ret = phy_write(phydev, 0x17, 0x0005); + if (ret) + return ret; + ret = phy_write(phydev, 0x14, 0x5C1B); + if (ret) + return ret; /* Program fraction FR_PLL_DIV1 */ - phy_write(phydev, 0x17, 0x029A); - phy_write(phydev, 0x14, 0x5C1D); + ret = phy_write(phydev, 0x17, 0x029A); + if (ret) + return ret; + ret = phy_write(phydev, 0x14, 0x5C1D); + if (ret) + return ret; /* Program fraction FR_PLL_DIV1 */ - phy_write(phydev, 0x17, 0xAAAA); - phy_write(phydev, 0x14, 0x5C1C); + ret = phy_write(phydev, 0x17, 0xAAAA); + if (ret) + return ret; + ret = phy_write(phydev, 0x14, 0x5C1C); + if (ret) + return ret; return 0; }