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[209.132.180.67]) by mx.google.com with ESMTP id f4si10946777plr.760.2017.12.05.01.34.01; Tue, 05 Dec 2017 01:34:01 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=jVzDQ/Qz; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753088AbdLEJd7 (ORCPT + 28 others); Tue, 5 Dec 2017 04:33:59 -0500 Received: from mail-wm0-f65.google.com ([74.125.82.65]:36573 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752954AbdLEJdx (ORCPT ); Tue, 5 Dec 2017 04:33:53 -0500 Received: by mail-wm0-f65.google.com with SMTP id b76so26150wmg.1 for ; Tue, 05 Dec 2017 01:33:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id; bh=HYsfUd9APITp32BCaGweK4HOt15WuBZ1GdnDmLcvMNA=; b=jVzDQ/QzW9I4jq9nBZIyKo9uaDs1sHj/hzjp0vVSqYfEydn5RRu0Upy5IN3itJdTmV kcxSL6kFDdir9EITMZicofyMjyggtHpP3ebHKVv594tQy8TW9O+sggYxN+83JsU+Vy4v uxJXgFfmLIuFSKXdvSU3880q6wuJo7y6fGuNI4aOCkJRlL7aVsW3Pg5J1Wn+Hpnj03/H DPxHyQAsdAIi7o8vV/yaKUOyCyJXD2KvPkpAuAzSTVKuhHvThZnN3PPgmn7p+4src7HY vgSTSqFBAfBsle8HtDTc5hYT2cnx7yg5fqeDkwscqduJwVeKSkAkDQ2nTiqgntSaB0gO kpXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=HYsfUd9APITp32BCaGweK4HOt15WuBZ1GdnDmLcvMNA=; b=H7faEma94gCRBuCHQc4w4LypcROCQgCKKjjROAr1P180dL0PthjdV79piBcLLITBeV iRS3Q+hAbNwHnDVuDzBfG8szbGtnieo8N8CbSmbk9x+IgBinccPlsjxX2pYVObNKmlf/ LP9nS43+1L2z/h/Nt/eUXN0Ll8UCbUDn8C2lB8GtyOTXj60YvIgxXVIb9eWENJFJJTcy WJ3OUDWynsCODgacTQa4f7gxumW4gWllVIQMp79upnDy1eD2wJGMA0JHmTlp83oWlB3X d8i0dirtvhpmtQYqWehuHb1eWqQjqcm+Usnd+ua4yIssn/4L1mWjC1mGUJJ5g+0knOT1 ZaEw== X-Gm-Message-State: AKGB3mIBjBeDmxhlFqPa3BRFXsW2p8qX7d0yZo9nc15fMhrvRINPSHlL oh7yV9CuAmsjcjLhZjb/AEQGwQ== X-Received: by 10.28.51.133 with SMTP id z127mr5801547wmz.84.1512466431620; Tue, 05 Dec 2017 01:33:51 -0800 (PST) Received: from boomer.baylibre.local ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id c12sm5853513wmi.43.2017.12.05.01.33.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 05 Dec 2017 01:33:51 -0800 (PST) From: Jerome Brunet To: Andrew Lunn , Florian Fainelli , Neil Armstrong Cc: netdev@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, Jerome Brunet Subject: [PATCH net-next] net: phy: meson-gxl: cleanup by defining the control registers Date: Tue, 5 Dec 2017 10:33:34 +0100 Message-Id: <20171205093334.8261-1-jbrunet@baylibre.com> X-Mailer: git-send-email 2.14.3 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Neil Armstrong Define registers and bits in meson-gxl PHY driver to make a bit more human friendly. No functional change Signed-off-by: Neil Armstrong Signed-off-by: Jerome Brunet --- drivers/net/phy/meson-gxl.c | 111 +++++++++++++++++++++++++++++++++++++------- 1 file changed, 93 insertions(+), 18 deletions(-) -- 2.14.3 diff --git a/drivers/net/phy/meson-gxl.c b/drivers/net/phy/meson-gxl.c index 1ea69b7585d9..82c11556605e 100644 --- a/drivers/net/phy/meson-gxl.c +++ b/drivers/net/phy/meson-gxl.c @@ -22,32 +22,107 @@ #include #include #include +#include + +#define TSTCNTL 0x14 +#define TSTREAD1 0x15 +#define TSTREAD2 0x16 +#define TSTWRITE 0x17 + +#define TSTCNTL_READ BIT(15) +#define TSTCNTL_WRITE BIT(14) +#define TSTCNTL_REG_BANK_SEL GENMASK(12, 11) +#define TSTCNTL_TEST_MODE BIT(10) +#define TSTCNTL_READ_ADDRESS GENMASK(9, 5) +#define TSTCNTL_WRITE_ADDRESS GENMASK(4, 0) + +#define BANK_ANALOG_DSP 0 +#define BANK_BIST 3 + +/* Analog/DSP Registers */ +#define A6_CONFIG_REG 0x17 + +/* BIST Registers */ +#define FR_PLL_CONTROL 0x1b +#define FR_PLL_DIV0 0x1c +#define FR_PLL_DIV1 0x1d + +#define A6_CONFIG_PLLMULX4ICH BIT(15) +#define A6_CONFIG_PLLBIASSEL BIT(14) +#define A6_CONFIG_PLLINTRATIO GENMASK(13, 12) +#define A6_CONFIG_PLLBUFITRIM GENMASK(11, 9) +#define A6_CONFIG_PLLCHTRIM GENMASK(8, 5) +#define A6_CONFIG_PLLCHBIASSEL BIT(4) +#define A6_CONFIG_PLLRSTVCOPD BIT(3) +#define A6_CONFIG_PLLCPOFF BIT(2) +#define A6_CONFIG_PLLPD BIT(1) +#define A6_CONFIG_PLL_SRC BIT(0) + +static inline int meson_gxl_write_reg(struct phy_device *phydev, + unsigned int bank, unsigned int reg, + uint16_t value) +{ + int ret; + + /* Enable Analog and DSP register Bank access by + * toggling TSTCNTL_TEST_MODE bit in the TSTCNTL register + */ + ret = phy_write(phydev, TSTCNTL, 0); + if (ret) + goto out; + ret = phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE); + if (ret) + goto out; + ret = phy_write(phydev, TSTCNTL, 0); + if (ret) + goto out; + ret = phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE); + if (ret) + goto out; + + ret = phy_write(phydev, TSTWRITE, value); + if (ret) + goto out; + + ret = phy_write(phydev, TSTCNTL, TSTCNTL_WRITE | + FIELD_PREP(TSTCNTL_REG_BANK_SEL, bank) | + TSTCNTL_TEST_MODE | + FIELD_PREP(TSTCNTL_WRITE_ADDRESS, reg)); + +out: + /* Close the bank access on our way out */ + phy_write(phydev, TSTCNTL, 0); + return ret; +} + static int meson_gxl_config_init(struct phy_device *phydev) { - /* Enable Analog and DSP register Bank access by */ - phy_write(phydev, 0x14, 0x0000); - phy_write(phydev, 0x14, 0x0400); - phy_write(phydev, 0x14, 0x0000); - phy_write(phydev, 0x14, 0x0400); + int ret; - /* Write Analog register 23 */ - phy_write(phydev, 0x17, 0x8E0D); - phy_write(phydev, 0x14, 0x4417); + /* Write PLL Configuration 1 */ + ret = meson_gxl_write_reg(phydev, BANK_ANALOG_DSP, A6_CONFIG_REG, + A6_CONFIG_PLLMULX4ICH | + FIELD_PREP(A6_CONFIG_PLLBUFITRIM, 7) | + A6_CONFIG_PLLRSTVCOPD | + A6_CONFIG_PLLCPOFF | + A6_CONFIG_PLL_SRC); + if (ret) + return ret; - /* Enable fractional PLL */ - phy_write(phydev, 0x17, 0x0005); - phy_write(phydev, 0x14, 0x5C1B); + /* Enable fractional PLL configuration */ + ret = meson_gxl_write_reg(phydev, BANK_BIST, FR_PLL_CONTROL, 0x5); + if (ret) + return ret; - /* Program fraction FR_PLL_DIV1 */ - phy_write(phydev, 0x17, 0x029A); - phy_write(phydev, 0x14, 0x5C1D); + ret = meson_gxl_write_reg(phydev, BANK_BIST, FR_PLL_DIV1, 0x029a); + if (ret) + return ret; - /* Program fraction FR_PLL_DIV1 */ - phy_write(phydev, 0x17, 0xAAAA); - phy_write(phydev, 0x14, 0x5C1C); + /* Program fraction FR_PLL_DIV0 */ + ret = meson_gxl_write_reg(phydev, BANK_BIST, FR_PLL_DIV0, 0xaaaa); - return 0; + return ret; } static struct phy_driver meson_gxl_phy[] = {