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[209.132.180.67]) by mx.google.com with ESMTP id t4si9362246pgf.33.2017.10.29.23.03.52; Sun, 29 Oct 2017 23:03:52 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=X5Uh9QjE; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752384AbdJ3GDv (ORCPT + 27 others); Mon, 30 Oct 2017 02:03:51 -0400 Received: from mail-pg0-f65.google.com ([74.125.83.65]:55122 "EHLO mail-pg0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752352AbdJ3GDs (ORCPT ); Mon, 30 Oct 2017 02:03:48 -0400 Received: by mail-pg0-f65.google.com with SMTP id l24so10668864pgu.11; Sun, 29 Oct 2017 23:03:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=nYS5XoJ3UKomt8MmyQyZMBs2kaPeYtUM+SszLWO0KLM=; b=X5Uh9QjEToc8MAIHa2pTxWElT+obNxUYHX1tEJ/HMkT1/BWRFULEAQjym4dy+YJhVm jimXh6Bo4+x08QffdY+/bS4sYYhjyZ77Hs5ID/vqnQpZUdmzkKEz2m562k0XGlzYF9wt Fz1rSfNowyC2YsZk+8e28uPyVppBbOf0SvkmuS6/4tRcDGXAkcaGnF3D07U1IpFfJCNB UCCtuX/Gzs6BtGWCfCKcJA7lk7dlpBK5afBQ5b3z7KRSh3NxS++g1tDcWRQ0veyXjZFk w5WbtijUz5a4KMwMcdxkKfHRm6Vztq18PyIbWcyxovsRxdaO2Pj3GAGVbw/h+RqAYG44 cj+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=nYS5XoJ3UKomt8MmyQyZMBs2kaPeYtUM+SszLWO0KLM=; b=CiSk2022tp5z4uWm845tRaJF+g9gj1sNYSNhy9dEwixd6uPGxzrXmlGPwc1Z3H+VQW KrinqimshNeLwWdh745DKJmkdFPhFza9DMuhTWwWmKLvx4BhDmSZRHJxP9D7IDZPAFUS HKcjVQfpDvUZr/IGuBbxUigDrM+WXn9BYGS7GU310CNNmb0SVmFwjXpXPVlstD8mv5au 9kl71F+NONPtRw9WMD9l+JeZLldYqSgd4rtkwb8W/7T8IfPtr8KkY4WdQn5vmmNxv4Ra oyF/CPPCGP0JlES3mk/kglMQ4H2JIDN3CjPebPKNTpX6dyNZ1lKtQ/rWt8FDWu0FXFc7 w2ag== X-Gm-Message-State: AMCzsaWiumZSI/2BKkgMpLNj64NaKi8c736mzFFI/yjtO9zqeg2FTmBT j8juE6+SuTkARWzh1pfxIt0= X-Received: by 10.84.241.15 with SMTP id a15mr6494982pll.199.1509343427569; Sun, 29 Oct 2017 23:03:47 -0700 (PDT) Received: from aurora.jms.id.au ([203.0.153.9]) by smtp.gmail.com with ESMTPSA id o22sm27504592pfi.85.2017.10.29.23.03.40 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 29 Oct 2017 23:03:45 -0700 (PDT) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Mon, 30 Oct 2017 16:33:38 +1030 From: Joel Stanley To: Lee Jones , Michael Turquette , Stephen Boyd Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Andrew Jeffery , Benjamin Herrenschmidt , Jeremy Kerr , Rick Altherr , Ryan Chen , Arnd Bergmann Subject: [PATCH v5 4/5] clk: aspeed: Register gated clocks Date: Mon, 30 Oct 2017 16:32:49 +1030 Message-Id: <20171030060250.701-5-joel@jms.id.au> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171030060250.701-1-joel@jms.id.au> References: <20171030060250.701-1-joel@jms.id.au> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The majority of the clocks in the system are gates paired with a reset controller that holds the IP in reset. This borrows from clk_hw_register_gate, but registers two 'gates', one to control the clock enable register and the other to control the reset IP. This allows us to enforce the ordering: 1. Place IP in reset 2. Enable clock 3. Delay 4. Release reset There are some gates that do not have an associated reset; these are handled by using -1 as the index for the reset. Reviewed-by: Andrew Jeffery Signed-off-by: Joel Stanley --- v5: - Add Andrew's Reviewed-by v4: - Drop useless 'disable clock' comment - Drop CLK_IS_BASIC flag - Fix 'there are a number of clocks...' comment - Pass device to clk registration functions - Check for errors when registering clk_hws v3: - Remove gates offset as gates are now at the start of the list --- drivers/clk/clk-aspeed.c | 131 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 131 insertions(+) -- 2.14.1 diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c index 8bf3f3767560..df5bc57a6ee2 100644 --- a/drivers/clk/clk-aspeed.c +++ b/drivers/clk/clk-aspeed.c @@ -211,6 +211,107 @@ static const struct aspeed_clk_soc_data ast2400_data = { .calc_pll = aspeed_ast2400_calc_pll, }; +static int aspeed_clk_enable(struct clk_hw *hw) +{ + struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); + unsigned long flags; + u32 clk = BIT(gate->clock_idx); + u32 rst = BIT(gate->reset_idx); + + spin_lock_irqsave(gate->lock, flags); + + if (gate->reset_idx >= 0) { + /* Put IP in reset */ + regmap_update_bits(gate->map, ASPEED_RESET_CTRL, rst, rst); + + /* Delay 100us */ + udelay(100); + } + + /* Enable clock */ + regmap_update_bits(gate->map, ASPEED_CLK_STOP_CTRL, clk, 0); + + if (gate->reset_idx >= 0) { + /* Delay 10ms */ + /* TODO: can we sleep here? */ + msleep(10); + + /* Take IP out of reset */ + regmap_update_bits(gate->map, ASPEED_RESET_CTRL, rst, 0); + } + + spin_unlock_irqrestore(gate->lock, flags); + + return 0; +} + +static void aspeed_clk_disable(struct clk_hw *hw) +{ + struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); + unsigned long flags; + u32 clk = BIT(gate->clock_idx); + + spin_lock_irqsave(gate->lock, flags); + + regmap_update_bits(gate->map, ASPEED_CLK_STOP_CTRL, clk, clk); + + spin_unlock_irqrestore(gate->lock, flags); +} + +static int aspeed_clk_is_enabled(struct clk_hw *hw) +{ + struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); + u32 clk = BIT(gate->clock_idx); + u32 reg; + + regmap_read(gate->map, ASPEED_CLK_STOP_CTRL, ®); + + return (reg & clk) ? 0 : 1; +} + +static const struct clk_ops aspeed_clk_gate_ops = { + .enable = aspeed_clk_enable, + .disable = aspeed_clk_disable, + .is_enabled = aspeed_clk_is_enabled, +}; + +static struct clk_hw *aspeed_clk_hw_register_gate(struct device *dev, + const char *name, const char *parent_name, unsigned long flags, + struct regmap *map, u8 clock_idx, u8 reset_idx, + u8 clk_gate_flags, spinlock_t *lock) +{ + struct aspeed_clk_gate *gate; + struct clk_init_data init; + struct clk_hw *hw; + int ret; + + gate = kzalloc(sizeof(*gate), GFP_KERNEL); + if (!gate) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.ops = &aspeed_clk_gate_ops; + init.flags = flags; + init.parent_names = parent_name ? &parent_name : NULL; + init.num_parents = parent_name ? 1 : 0; + + gate->map = map; + gate->clock_idx = clock_idx; + gate->reset_idx = reset_idx; + gate->flags = clk_gate_flags; + gate->lock = lock; + gate->hw.init = &init; + + hw = &gate->hw; + ret = clk_hw_register(dev, hw); + if (ret) { + kfree(gate); + hw = ERR_PTR(ret); + } + + return hw; +} + static int aspeed_clk_probe(struct platform_device *pdev) { const struct aspeed_clk_soc_data *soc_data; @@ -218,6 +319,7 @@ static int aspeed_clk_probe(struct platform_device *pdev) struct regmap *map; struct clk_hw *hw; u32 val, rate; + int i; map = syscon_node_to_regmap(dev->of_node); if (IS_ERR(map)) { @@ -290,6 +392,35 @@ static int aspeed_clk_probe(struct platform_device *pdev) return PTR_ERR(hw); aspeed_clk_data->hws[ASPEED_CLK_BCLK] = hw; + /* + * TODO: There are a number of clocks that not included in this driver + * as more information is required: + * D2-PLL + * D-PLL + * YCLK + * RGMII + * RMII + * UART[1..5] clock source mux + * Video Engine (ECLK) mux and clock divider + */ + + for (i = 0; i < ARRAY_SIZE(aspeed_gates); i++) { + const struct aspeed_gate_data *gd = &aspeed_gates[i]; + + hw = aspeed_clk_hw_register_gate(dev, + gd->name, + gd->parent_name, + gd->flags, + map, + gd->clock_idx, + gd->reset_idx, + CLK_GATE_SET_TO_DISABLE, + &aspeed_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_clk_data->hws[i] = hw; + } + return 0; };