From patchwork Wed Oct 18 11:44:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 116272 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp5966127qgn; Wed, 18 Oct 2017 04:48:38 -0700 (PDT) X-Received: by 10.98.10.153 with SMTP id 25mr14326175pfk.60.1508327318783; Wed, 18 Oct 2017 04:48:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508327318; cv=none; d=google.com; s=arc-20160816; b=fdTmhxn/OroKMjbuQa2ypEInbIygdgaxCMjfEPb+QNz+Q0qvuPyNFjbxKjufoWDsnw m3kBqpoJDj3ZU+20VuIFa6vOym5HrgK/SrZabjRr7hB657vlD6O+Bx5k7Zg5xZGKWt8L cQec+mcUjj5aum01pOUCc+Z9qPKELihOzHMTIgx/xxHJJTUbGPvvF1dXgFvyKdRuFFTZ 599XOPAqN4enXzUx0maSK50Tx9wLUn2JMJwuQ5behykfckGIiB6F70XjyWYzKvbfYSew rnWMu8WtIsj8mNtb4ixF88dgiOzEkeoTvOBDF1/6W4EQeCJTBldUdRbs9hQvQ0tKbN2K dnJA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=4359aIbDyeAzMYI4UIa0MNdQ60F1ZYcchUvlj6q41ug=; b=R16a6kb/pZ65JRckDhwjolsvR2XVIXtDoxq0BD8t/jvXBC36TwJn875AhhlGfo2/rR dzQafKdQcrz1sGh5W/6hwhQRowsMDvRu+X1RCuW2mbJDknGCQ212R3aTTMBokBe5ewQ+ b8Y97Jy1OmuBgBjYlxoyYaCn16v4Oej8YKvysEpvMYFD4Hl4DSwFXJYBW90Y6Pp2gelG s6Jk7zGTy/SewJbI4IzghYxtSxK8FDCwiWA/znKtdbi6mjaEqZ3c+13TCoHBMJg29nk2 hN55mwmp/ovD1R4GXuuy1jc3SDAgK67hJYVRF4AXUSeLiR/aOM70jBdTagc+VEbQx/cs t6hw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=oRjQJTyr; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o15si6896216pgq.475.2017.10.18.04.48.38; Wed, 18 Oct 2017 04:48:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=oRjQJTyr; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932549AbdJRLrW (ORCPT + 27 others); Wed, 18 Oct 2017 07:47:22 -0400 Received: from mail-wr0-f193.google.com ([209.85.128.193]:45545 "EHLO mail-wr0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932406AbdJRLrS (ORCPT ); Wed, 18 Oct 2017 07:47:18 -0400 Received: by mail-wr0-f193.google.com with SMTP id k7so4706861wre.2; Wed, 18 Oct 2017 04:47:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4359aIbDyeAzMYI4UIa0MNdQ60F1ZYcchUvlj6q41ug=; b=oRjQJTyrBDP/biSLycJmz2Rr1Lau2L5OvrxLfeQ+tuPaPJIbbNZvJ6XBRs7WhwUxWA jGQ1JSF8HPFmPfnHP+A6VlWUKDV9v7Lm50yiBoGNMxmDbD2iwCn2EE55HLVf+LcfWk6T SwakVW424pDR6Ym3VxjoHz3pLmavbJ6EDzHNKVHPCJ5rcwjxFfRGTZb18EqsItmShL3U du1BJQRare0oE42TCNMV6mIoMMUU3ccl6zrhJZP/yi8ZkasqALlMwKYd3/xOuZnGP4kj xyzFgEP++jiC2badhOeMTBBLpc2kW+6KumBlRr+8SemF9035NUvvluPBKn42tzXQljQn UvVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4359aIbDyeAzMYI4UIa0MNdQ60F1ZYcchUvlj6q41ug=; b=WIyL+J5y8Ypyp8FU0nVqjBGdrd+oUc4ljkpxpjZD4SQ1qI7omlgJA5233uyutSkCFH 9Qerrw/thebnOeuwmV0YC0Fa2alf+GQ5t70o1PzMsN9uGEXMES9oJgDMe4G8DXGf75oW wYsuKOGFEYzeCKYUg/QXSzVaqaWT07CYwvq/CEb0xAsARonRqNHIH1NWE+xJfJqsgOtz lpHtCYJi3Znmad5iVyJdPG0jU/38/1gcHE0+sBfMM7uUo71V4vNh3jE93GR41s8Wfc5o 249pG6ZUrTsddF2zLbW1GP3GMtTBnU7mqdPco9T8Ldiwur+NgyQD8AQawerBJLH0j62o EIbA== X-Gm-Message-State: AMCzsaXf10aQcbXl7uqgTHJmnopOjLxhXhhF80WApPlEzimUVzAHTGpt cX61ycfDF/zLSHs7Mx9kZHc= X-Google-Smtp-Source: ABhQp+QXA/7vucDR8+5ncv4Cvey0DCwmpiqwJ7zm+lECmO969utxKlX716BJlufhuxBtaiLjj21hTQ== X-Received: by 10.223.136.246 with SMTP id g51mr6082593wrg.226.1508327236961; Wed, 18 Oct 2017 04:47:16 -0700 (PDT) Received: from Red.local (LFbn-MAR-1-580-96.w90-118.abo.wanadoo.fr. [90.118.159.96]) by smtp.googlemail.com with ESMTPSA id 61sm8444391wrg.58.2017.10.18.04.47.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 18 Oct 2017 04:47:16 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com, frowand.list@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Corentin Labbe Subject: [PATCH v7 05/10] dt-bindings: net: dwmac-sun8i: update documentation about integrated PHY Date: Wed, 18 Oct 2017 13:44:53 +0200 Message-Id: <20171018114458.17891-6-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171018114458.17891-1-clabbe.montjoie@gmail.com> References: <20171018114458.17891-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch add documentation about the MDIO switch used on sun8i-h3-emac for integrated PHY. Signed-off-by: Corentin Labbe --- .../devicetree/bindings/net/dwmac-sun8i.txt | 139 +++++++++++++++++++-- 1 file changed, 127 insertions(+), 12 deletions(-) -- 2.13.6 diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt index 725f3b187886..0ae7d2096375 100644 --- a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt +++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt @@ -4,18 +4,18 @@ This device is a platform glue layer for stmmac. Please see stmmac.txt for the other unchanged properties. Required properties: -- compatible: should be one of the following string: +- compatible: must be one of the following string: "allwinner,sun8i-a83t-emac" "allwinner,sun8i-h3-emac" "allwinner,sun8i-v3s-emac" "allwinner,sun50i-a64-emac" - reg: address and length of the register for the device. - interrupts: interrupt for the device -- interrupt-names: should be "macirq" +- interrupt-names: must be "macirq" - clocks: A phandle to the reference clock for this device -- clock-names: should be "stmmaceth" +- clock-names: must be "stmmaceth" - resets: A phandle to the reset control for this device -- reset-names: should be "stmmaceth" +- reset-names: must be "stmmaceth" - phy-mode: See ethernet.txt - phy-handle: See ethernet.txt - #address-cells: shall be 1 @@ -39,23 +39,38 @@ Optional properties for the following compatibles: - allwinner,leds-active-low: EPHY LEDs are active low Required child node of emac: -- mdio bus node: should be named mdio +- mdio bus node: with compatible "snps,dwmac-mdio" Required properties of the mdio node: - #address-cells: shall be 1 - #size-cells: shall be 0 -The device node referenced by "phy" or "phy-handle" should be a child node +The device node referenced by "phy" or "phy-handle" must be a child node of the mdio node. See phy.txt for the generic PHY bindings. -Required properties of the phy node with the following compatibles: +The following compatibles require that the mdio node have a mdio-mux child +node called "mdio-mux": + - "allwinner,sun8i-h3-emac" + - "allwinner,sun8i-v3s-emac": +Required properties for the mdio-mux node: + - compatible = "mdio-mux", "allwinner,sun8i-h3-mdio-mux" + - one child mdio for the integrated mdio with the compatible + "allwinner,sun8i-h3-mdio-internal" + - one child mdio for the external mdio if present (V3s have none) +Required properties for the mdio-mux children node: + - reg: 1 for internal MDIO bus, 2 for external MDIO bus + +The following compatibles require a PHY node representing the integrated +PHY, under the integrated MDIO bus node if an mdio-mux node is used: - "allwinner,sun8i-h3-emac", - "allwinner,sun8i-v3s-emac": + +Required properties of the integrated phy node: - clocks: a phandle to the reference clock for the EPHY - resets: a phandle to the reset control for the EPHY +- Must be a child of the integrated mdio -Example: - +Example with integrated PHY: emac: ethernet@1c0b000 { compatible = "allwinner,sun8i-h3-emac"; syscon = <&syscon>; @@ -72,13 +87,113 @@ emac: ethernet@1c0b000 { phy-handle = <&int_mii_phy>; phy-mode = "mii"; allwinner,leds-active-low; + + mdio0: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + mdio-mux { + compatible = "mdio-mux", "allwinner,sun8i-h3-mdio-mux"; + #address-cells = <1>; + #size-cells = <0>; + + int_mdio: mdio@1 { + compatible = "allwinner,sun8i-h3-mdio-internal"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + int_mii_phy: ethernet-phy@1 { + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + phy-is-integrated; + }; + }; + ext_mdio: mdio@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; +}; + +Example with external PHY: +emac: ethernet@1c0b000 { + compatible = "allwinner,sun8i-h3-emac"; + syscon = <&syscon>; + reg = <0x01c0b000 0x104>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + #address-cells = <1>; + #size-cells = <0>; + + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + allwinner,leds-active-low; + + mdio0: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + mdio-mux { + compatible = "mdio-mux", "allwinner,sun8i-h3-mdio-mux"; + #address-cells = <1>; + #size-cells = <0>; + + int_mdio: mdio@1 { + compatible = "allwinner,sun8i-h3-mdio-internal"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + int_mii_phy: ethernet-phy@1 { + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + }; + }; + ext_mdio: mdio@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + ext_rgmii_phy: ethernet-phy@1 { + reg = <1>; + }; + }: + }; + }; +}; + +Example with SoC without integrated PHY + +emac: ethernet@1c0b000 { + compatible = "allwinner,sun8i-a83t-emac"; + syscon = <&syscon>; + reg = <0x01c0b000 0x104>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + #address-cells = <1>; + #size-cells = <0>; + + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + mdio: mdio { + compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; - int_mii_phy: ethernet-phy@1 { + ext_rgmii_phy: ethernet-phy@1 { reg = <1>; - clocks = <&ccu CLK_BUS_EPHY>; - resets = <&ccu RST_BUS_EPHY>; }; }; };