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[209.132.180.67]) by mx.google.com with ESMTP id v32si2737079plb.415.2017.10.15.21.02.04; Sun, 15 Oct 2017 21:02:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751713AbdJPECB (ORCPT + 27 others); Mon, 16 Oct 2017 00:02:01 -0400 Received: from mx2.suse.de ([195.135.220.15]:58020 "EHLO mx2.suse.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750817AbdJPEB5 (ORCPT ); Mon, 16 Oct 2017 00:01:57 -0400 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay1.suse.de (charybdis-ext.suse.de [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id 8863EAE91; Mon, 16 Oct 2017 04:01:55 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Bizon , =?utf-8?q?An?= =?utf-8?q?dreas_F=C3=A4rber?= , info@synology.com, Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , devicetree@vger.kernel.org Subject: [PATCH 3/5] arm64: dts: realtek: Add RTD1293 and Synology DS418j Date: Mon, 16 Oct 2017 06:01:48 +0200 Message-Id: <20171016040150.23400-4-afaerber@suse.de> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171016040150.23400-1-afaerber@suse.de> References: <20171016040150.23400-1-afaerber@suse.de> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add Device Trees for RTD1293 SoC and Synology DiskStation DS481j NAS. Cc: info@synology.com Signed-off-by: Andreas Färber --- arch/arm64/boot/dts/realtek/Makefile | 2 + arch/arm64/boot/dts/realtek/rtd1293-ds418j.dts | 31 ++++++++++++++ arch/arm64/boot/dts/realtek/rtd1293.dtsi | 56 ++++++++++++++++++++++++++ 3 files changed, 89 insertions(+) create mode 100644 arch/arm64/boot/dts/realtek/rtd1293-ds418j.dts create mode 100644 arch/arm64/boot/dts/realtek/rtd1293.dtsi -- 2.13.6 diff --git a/arch/arm64/boot/dts/realtek/Makefile b/arch/arm64/boot/dts/realtek/Makefile index f43d0209ded7..25c795272507 100644 --- a/arch/arm64/boot/dts/realtek/Makefile +++ b/arch/arm64/boot/dts/realtek/Makefile @@ -1,3 +1,5 @@ +dtb-$(CONFIG_ARCH_REALTEK) += rtd1293-ds418j.dtb + dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-probox2-ava.dtb dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-zidoo-x9s.dtb diff --git a/arch/arm64/boot/dts/realtek/rtd1293-ds418j.dts b/arch/arm64/boot/dts/realtek/rtd1293-ds418j.dts new file mode 100644 index 000000000000..0f17bbb5aabb --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1293-ds418j.dts @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2017 Andreas Färber + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +/dts-v1/; + +#include "rtd1293.dtsi" + +/ { + compatible = "synology,ds418j", "realtek,rtd1293"; + model = "Synology DiskStation DS418j"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/realtek/rtd1293.dtsi b/arch/arm64/boot/dts/realtek/rtd1293.dtsi new file mode 100644 index 000000000000..403f0c55ace0 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1293.dtsi @@ -0,0 +1,56 @@ +/* + * Realtek RTD1293 SoC + * + * Copyright (c) 2017 Andreas Färber + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +#include "rtd129x.dtsi" + +/ { + compatible = "realtek,rtd1293"; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x9801aa44>; + next-level-cache = <&l2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x9801aa44>; + next-level-cache = <&l2>; + }; + + l2: l2-cache { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; + +&arm_pmu { + interrupt-affinity = <&cpu0>, <&cpu1>; +};