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[209.132.180.67]) by mx.google.com with ESMTP id d19si8134113pgn.805.2017.10.10.03.16.33; Tue, 10 Oct 2017 03:16:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=L7HECNoA; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756065AbdJJKQc (ORCPT + 26 others); Tue, 10 Oct 2017 06:16:32 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:36070 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751398AbdJJKQ3 (ORCPT ); Tue, 10 Oct 2017 06:16:29 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v9AAGN9i021037; Tue, 10 Oct 2017 05:16:23 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1507630583; bh=xl0yCLpAyGS/2QK2anUNdHehhD01vqDdG4Sb9/Nqlpk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=L7HECNoAi6xLIah3u8IgoHerPMIBsMpznsWDyF3rFhq2PKZCHGCJsbnnayxTD/vii DT8bZ2w7i7pxym0muhc4JQQGP5OUOb0sz+AVy6gvVuHVUmIvhLpUoy/hsmHWIapD+s FhjKPtaT9Z2i+zuEfu5n4Glm8TnwBd1dOYATtA2I= Received: from DLEE101.ent.ti.com (dlee101.ent.ti.com [157.170.170.31]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v9AAGNPr006552; Tue, 10 Oct 2017 05:16:23 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Tue, 10 Oct 2017 05:16:23 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Tue, 10 Oct 2017 05:16:23 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v9AAG8ul025359; Tue, 10 Oct 2017 05:16:20 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Rob Herring , Mark Rutland CC: Kishon Vijay Abraham I , , , , , Subject: [PATCH 4/4] PCI: dwc: pci-dra7xx: Enable x2 mode support Date: Tue, 10 Oct 2017 15:46:06 +0530 Message-ID: <20171010101606.15951-5-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171010101606.15951-1-kishon@ti.com> References: <20171010101606.15951-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Perform syscon configurations to get x2 mode to working in dra74x (and dra76x). Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sekhar Nori --- drivers/pci/dwc/pci-dra7xx.c | 68 ++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 66 insertions(+), 2 deletions(-) -- 2.11.0 diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c index 78a87a8f1362..a43c904310f3 100644 --- a/drivers/pci/dwc/pci-dra7xx.c +++ b/drivers/pci/dwc/pci-dra7xx.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -83,6 +84,9 @@ #define MSI_REQ_GRANT BIT(0) #define MSI_VECTOR_SHIFT 7 +#define PCIE_1LANE_2LANE_SELECTION BIT(13) +#define PCIE_B1C0_MODE_SEL BIT(2) + struct dra7xx_pcie { struct dw_pcie *pci; void __iomem *base; /* DT ti_conf */ @@ -95,6 +99,10 @@ struct dra7xx_pcie { struct dra7xx_pcie_of_data { enum dw_pcie_device_mode mode; + u32 b1co_mode_sel_mask; +}; + +struct dra7xx_pcie_data { }; #define to_dra7xx_pcie(x) dev_get_drvdata((x)->dev) @@ -533,6 +541,16 @@ static const struct dra7xx_pcie_of_data dra7xx_pcie_ep_of_data = { .mode = DW_PCIE_EP_TYPE, }; +static const struct dra7xx_pcie_of_data dra746_pcie_rc_of_data = { + .b1co_mode_sel_mask = BIT(2), + .mode = DW_PCIE_RC_TYPE, +}; + +static const struct dra7xx_pcie_of_data dra746_pcie_ep_of_data = { + .b1co_mode_sel_mask = BIT(2), + .mode = DW_PCIE_EP_TYPE, +}; + static const struct of_device_id of_dra7xx_pcie_match[] = { { .compatible = "ti,dra7-pcie", @@ -544,11 +562,11 @@ static const struct of_device_id of_dra7xx_pcie_match[] = { }, { .compatible = "ti,dra746-pcie-rc", - .data = &dra7xx_pcie_rc_of_data, + .data = &dra746_pcie_rc_of_data, }, { .compatible = "ti,dra746-pcie-ep", - .data = &dra7xx_pcie_ep_of_data, + .data = &dra746_pcie_ep_of_data, }, { .compatible = "ti,dra726-pcie-rc", @@ -603,6 +621,44 @@ static int dra7xx_pcie_ep_unaligned_memaccess(struct device *dev) return ret; } +static int dra7xx_pcie_configure_two_lane(struct device *dev, + u32 b1co_mode_sel_mask) +{ + struct device_node *np = dev->of_node; + struct regmap *pcie_syscon; + unsigned int pcie_reg; + + pcie_syscon = syscon_regmap_lookup_by_phandle(np, "syscon-lane-conf"); + if (IS_ERR(pcie_syscon)) { + dev_err(dev, "unable to get syscon-lane-conf\n"); + return -EINVAL; + } + + if (of_property_read_u32_index(np, "syscon-lane-conf", 1, &pcie_reg)) { + dev_err(dev, "couldn't get lane configuration reg offset\n"); + return -EINVAL; + } + + regmap_update_bits(pcie_syscon, pcie_reg, PCIE_1LANE_2LANE_SELECTION, + PCIE_1LANE_2LANE_SELECTION); + + pcie_syscon = syscon_regmap_lookup_by_phandle(np, "syscon-lane-sel"); + if (IS_ERR(pcie_syscon)) { + dev_err(dev, "unable to get syscon-lane-sel\n"); + return -EINVAL; + } + + if (of_property_read_u32_index(np, "syscon-lane-sel", 1, &pcie_reg)) { + dev_err(dev, "couldn't get lane selection reg offset\n"); + return -EINVAL; + } + + regmap_update_bits(pcie_syscon, pcie_reg, b1co_mode_sel_mask, + PCIE_B1C0_MODE_SEL); + + return 0; +} + static int __init dra7xx_pcie_probe(struct platform_device *pdev) { u32 reg; @@ -624,6 +680,7 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev) const struct of_device_id *match; const struct dra7xx_pcie_of_data *data; enum dw_pcie_device_mode mode; + u32 b1co_mode_sel_mask; match = of_match_device(of_match_ptr(of_dra7xx_pcie_match), dev); if (!match) @@ -631,6 +688,7 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev) data = (struct dra7xx_pcie_of_data *)match->data; mode = (enum dw_pcie_device_mode)data->mode; + b1co_mode_sel_mask = data->b1co_mode_sel_mask; dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL); if (!dra7xx) @@ -689,6 +747,12 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev) dra7xx->pci = pci; dra7xx->phy_count = phy_count; + if (phy_count == 2) { + ret = dra7xx_pcie_configure_two_lane(dev, b1co_mode_sel_mask); + if (ret < 0) + goto err_link; + } + ret = dra7xx_pcie_enable_phy(dra7xx); if (ret) { dev_err(dev, "failed to enable phy\n");