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[209.132.180.67]) by mx.google.com with ESMTP id s36si8868135pld.502.2017.10.10.03.17.15; Tue, 10 Oct 2017 03:17:15 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=imG29VCU; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755967AbdJJKRO (ORCPT + 26 others); Tue, 10 Oct 2017 06:17:14 -0400 Received: from fllnx209.ext.ti.com ([198.47.19.16]:32281 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754416AbdJJKRK (ORCPT ); Tue, 10 Oct 2017 06:17:10 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v9AAGPCV011495; Tue, 10 Oct 2017 05:16:25 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1507630585; bh=upBTM2RVAPnVNMsbc14f8HIV+fpYjZ7Y3XBMS6bkb2o=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=imG29VCUevKAruLPOWLwVz+1BfMZU/RmjykTfH05es4F0mqlAaj1lWBalbZ/N0fst 2gvLUfTcB0BTYpjjtWXTR8R/wUCxiAyjbzFe9qYUgSEZgX3RkfsVj0qOdo2vnBRwbf efu+gJ0r0Wou+SiqsPrmsqCn5pu69e/iG+isv8hg= Received: from DLEE101.ent.ti.com (dlee101.ent.ti.com [157.170.170.31]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v9AAGKVt006513; Tue, 10 Oct 2017 05:16:20 -0500 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Tue, 10 Oct 2017 05:16:20 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Tue, 10 Oct 2017 05:16:20 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v9AAG8uk025359; Tue, 10 Oct 2017 05:16:17 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Rob Herring , Mark Rutland CC: Kishon Vijay Abraham I , , , , , Subject: [PATCH 3/4] PCI: dwc: dra7xx: Add support for SoC specific compatible strings Date: Tue, 10 Oct 2017 15:46:05 +0530 Message-ID: <20171010101606.15951-4-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171010101606.15951-1-kishon@ti.com> References: <20171010101606.15951-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org dra74x/dra76x and dra72x has separate compatible strings. Add support for these compatible strings in pci-dra7xx driver. This is a preparatory patch for adding 2-lane mode support and dra74/dra72 should add it's own driver data for 2-lane mode configuration. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sekhar Nori --- drivers/pci/dwc/pci-dra7xx.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) -- 2.11.0 diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c index 362607f727ee..78a87a8f1362 100644 --- a/drivers/pci/dwc/pci-dra7xx.c +++ b/drivers/pci/dwc/pci-dra7xx.c @@ -542,6 +542,22 @@ static const struct of_device_id of_dra7xx_pcie_match[] = { .compatible = "ti,dra7-pcie-ep", .data = &dra7xx_pcie_ep_of_data, }, + { + .compatible = "ti,dra746-pcie-rc", + .data = &dra7xx_pcie_rc_of_data, + }, + { + .compatible = "ti,dra746-pcie-ep", + .data = &dra7xx_pcie_ep_of_data, + }, + { + .compatible = "ti,dra726-pcie-rc", + .data = &dra7xx_pcie_rc_of_data, + }, + { + .compatible = "ti,dra726-pcie-ep", + .data = &dra7xx_pcie_ep_of_data, + }, {}, };