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[209.132.180.67]) by mx.google.com with ESMTP id b8si1167690pfh.564.2017.10.10.03.16.52; Tue, 10 Oct 2017 03:16:52 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=tNMGM4Kc; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756077AbdJJKQv (ORCPT + 26 others); Tue, 10 Oct 2017 06:16:51 -0400 Received: from lelnx194.ext.ti.com ([198.47.27.80]:32510 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755871AbdJJKQW (ORCPT ); Tue, 10 Oct 2017 06:16:22 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v9AAGHsD023842; Tue, 10 Oct 2017 05:16:17 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1507630577; bh=/Z+kTpajQhSfkRmVd7pqZCx1dFCAqF8vjBEsFpH9i2M=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=tNMGM4KcxCcNnhDOUXjhvE4bNYdtlQ1zXGpNNPAVoGF0R5aeB0PYyRlTyVZR4kpKI /9xBoO3G7vJ5AbdXyiSjuO3+zP+68AgZXfYijw1Mkue73a9Uv3Bi+TOtFh814gOuMK n/R5FE4KqGvJlMxlGuDVp4VUoa9VXN40JkkNtGXQ= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v9AAGHU0006454; Tue, 10 Oct 2017 05:16:17 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Tue, 10 Oct 2017 05:16:17 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Tue, 10 Oct 2017 05:16:17 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v9AAG8uj025359; Tue, 10 Oct 2017 05:16:14 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Rob Herring , Mark Rutland CC: Kishon Vijay Abraham I , , , , , Subject: [PATCH 2/4] dt-bindings: PCI: dra7xx: Add properties to enable x2 lane in dra7 Date: Tue, 10 Oct 2017 15:46:04 +0530 Message-ID: <20171010101606.15951-3-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171010101606.15951-1-kishon@ti.com> References: <20171010101606.15951-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add syscon properties required for configuring PCIe in x2 lane mode. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sekhar Nori --- Documentation/devicetree/bindings/pci/ti-pci.txt | 4 ++++ 1 file changed, 4 insertions(+) -- 2.11.0 diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt index 82cb875e4cec..455cb74a475c 100644 --- a/Documentation/devicetree/bindings/pci/ti-pci.txt +++ b/Documentation/devicetree/bindings/pci/ti-pci.txt @@ -13,6 +13,10 @@ PCIe DesignWare Controller - ti,hwmods : Name of the hwmod associated to the pcie, "pcie", where is the instance number of the pcie from the HW spec. - num-lanes as specified in ../designware-pcie.txt + - syscon-lane-conf : phandle/offset pair. Phandle to the system control module and the + register offset to specify 1 lane or 2 lane. + - syscon-lane-sel : phandle/offset pair. Phandle to the system control module and the + register offset to specify lane selection. HOST MODE =========