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[209.132.180.67]) by mx.google.com with ESMTP id b3si6675079pgr.350.2017.10.02.23.56.39; Mon, 02 Oct 2017 23:56:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=FzwtrsUL; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751265AbdJCG4i (ORCPT + 26 others); Tue, 3 Oct 2017 02:56:38 -0400 Received: from mail-pf0-f196.google.com ([209.85.192.196]:37873 "EHLO mail-pf0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750812AbdJCG4g (ORCPT ); Tue, 3 Oct 2017 02:56:36 -0400 Received: by mail-pf0-f196.google.com with SMTP id e69so8119412pfg.4; Mon, 02 Oct 2017 23:56:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=4lUaI30R32aYky+YmHAhMPFkS08klxHK91VU3kv527M=; b=FzwtrsULDufHNGvN8XAx84zunDE2fD4pD+RiSeXeRUYxsTaDzERALesIgxLXEYY2s/ 7UhVY1yYfyTdltuG1zY8xLrDTGovVI50or1ghAKXy+rnkVRN3JXQ/E6bOTd0iv/sJOjV 2tj0bbUOYDqiQnzA8jDIUqhilJRuqBg7b4kdNQV9HHqMu1UnDjWjORI+s69kGKwVb6jl CciBxFVqV0kln4zVGnN3qJCG4LOTXAoz4eqYPm1y9WrKIO5uI8JmCy4ofERfwUU34WYp EWQ5d2lijgvsNHNQn4BKvbOPBNTl1P9212CK9+JFo/t9dd3fLKvPLsX9WwD65VzVEdTj yp4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=4lUaI30R32aYky+YmHAhMPFkS08klxHK91VU3kv527M=; b=YrY00uIbYBYnMkUplORMsQmRmmleLoy48dEG8MEHgHjyUBw2yJJ6glvrVP6psrHMVp Wi4yPSdQpnsz/Epl4WNTJ6oBI7o3LOnabEAhjfr0saozR5y+nCTabzrKZkNuzwOyKEtS bCRaD/P114beZjg7xgboWVaSYruo9Aw8US/AVBpZthAM91eyJXzOOmYw2cvB/QRJnnoO hZ7IVSgFzElSqtKPBpayPj9Ay1ohP9fdnKNYe3GfaJ2J5ZIGyW/nC4n4vtuR/VKkYlrk YX7pCG+i3S8ee2CKjUwMap0zR8DzicfWuoDkSoHmTsMlcBL54YLDY8Aiz+8HBAhSbRn5 VHSw== X-Gm-Message-State: AHPjjUgRtrbFqlSOhW7iS4eeFTOdS/lQ656Z3kpyShh59/larAEWotH8 2lYKD5tpghpoc+u86FVysaw= X-Google-Smtp-Source: AOwi7QBClOF7xygbkumngpp3pUveXOkITGA3hY64VsDkZKaDA1/BOn3L+XFjUi0mxgqniuZy1fv/WQ== X-Received: by 10.84.235.9 with SMTP id o9mr15797564plk.8.1507013795681; Mon, 02 Oct 2017 23:56:35 -0700 (PDT) Received: from aurora.jms.id.au ([203.0.153.9]) by smtp.gmail.com with ESMTPSA id e133sm20245887pfh.177.2017.10.02.23.56.29 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 02 Oct 2017 23:56:34 -0700 (PDT) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Tue, 03 Oct 2017 17:26:26 +1030 From: Joel Stanley To: Lee Jones , Michael Turquette , Stephen Boyd Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Andrew Jeffery , Benjamin Herrenschmidt , Jeremy Kerr , Rick Altherr , Ryan Chen , Arnd Bergmann Subject: [PATCH v4 3/5] clk: aspeed: Add platform driver and register PLLs Date: Tue, 3 Oct 2017 17:25:38 +1030 Message-Id: <20171003065540.11722-4-joel@jms.id.au> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171003065540.11722-1-joel@jms.id.au> References: <20171003065540.11722-1-joel@jms.id.au> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This registers a platform driver to set up all of the non-core clocks. The clocks that have configurable rates are now registered. Signed-off-by: Joel Stanley -- v4: - Add eclk div table to fix ast2500 calculation - Add defines to document the BIT() macros - Pass dev where we can when registering clocks - Check for errors when registering clk_hws v3: - Fix bclk and eclk calculation - Seperate out ast2400 and ast25000 for pll calculation Signed-off-by: Joel Stanley --- drivers/clk/clk-aspeed.c | 163 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 163 insertions(+) -- 2.14.1 diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c index d39cf51a5114..adb295292189 100644 --- a/drivers/clk/clk-aspeed.c +++ b/drivers/clk/clk-aspeed.c @@ -14,6 +14,8 @@ #include #include #include +#include +#include #include #include #include @@ -114,6 +116,32 @@ static const struct aspeed_gate_data aspeed_gates[] __initconst = { [ASPEED_CLK_GATE_LHCCLK] = { 28, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */ }; +static const char * const eclk_parents[] = {"d1pll", "hpll", "mpll"}; + +static const struct clk_div_table ast2500_eclk_div_table[] = { + { 0x0, 2 }, + { 0x1, 2 }, + { 0x2, 3 }, + { 0x3, 4 }, + { 0x4, 5 }, + { 0x5, 6 }, + { 0x6, 7 }, + { 0x7, 8 }, + { 0 } +}; + +static const struct clk_div_table ast2500_mac_div_table[] = { + { 0x0, 4 }, /* Yep, really. Aspeed confirmed this is correct */ + { 0x1, 4 }, + { 0x2, 6 }, + { 0x3, 8 }, + { 0x4, 10 }, + { 0x5, 12 }, + { 0x6, 14 }, + { 0x7, 16 }, + { 0 } +}; + static const struct clk_div_table ast2400_div_table[] = { { 0x0, 2 }, { 0x1, 4 }, @@ -179,6 +207,141 @@ static struct clk_hw *aspeed_ast2500_calc_pll(const char *name, u32 val) mult, div); } +struct aspeed_clk_soc_data { + const struct clk_div_table *div_table; + const struct clk_div_table *mac_div_table; + const struct clk_div_table *eclk_div_table; + struct clk_hw *(*calc_pll)(const char *name, u32 val); +}; + +static const struct aspeed_clk_soc_data ast2500_data = { + .div_table = ast2500_div_table, + .mac_div_table = ast2500_mac_div_table, + .eclk_div_table = ast2500_eclk_div_table, + .calc_pll = aspeed_ast2500_calc_pll, +}; + +static const struct aspeed_clk_soc_data ast2400_data = { + .div_table = ast2400_div_table, + .mac_div_table = ast2400_div_table, + .eclk_div_table = ast2400_div_table, + .calc_pll = aspeed_ast2400_calc_pll, +}; + +static int aspeed_clk_probe(struct platform_device *pdev) +{ + const struct aspeed_clk_soc_data *soc_data; + struct device *dev = &pdev->dev; + struct regmap *map; + struct clk_hw *hw; + u32 val, rate; + + map = syscon_node_to_regmap(dev->of_node); + if (IS_ERR(map)) { + dev_err(dev, "no syscon regmap\n"); + return PTR_ERR(map); + } + + /* SoC generations share common layouts but have different divisors */ + soc_data = of_device_get_match_data(dev); + if (!soc_data) { + dev_err(dev, "no match data for platform\n"); + return -EINVAL; + } + + /* UART clock div13 setting */ + regmap_read(map, ASPEED_MISC_CTRL, &val); + if (val & UART_DIV13_EN) + rate = 24000000 / 13; + else + rate = 24000000; + /* TODO: Find the parent data for the uart clock */ + hw = clk_hw_register_fixed_rate(dev, "uart", NULL, 0, rate); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_clk_data->hws[ASPEED_CLK_UART] = hw; + + /* + * Memory controller (M-PLL) PLL. This clock is configured by the + * bootloader, and is exposed to Linux as a read-only clock rate. + */ + regmap_read(map, ASPEED_MPLL_PARAM, &val); + hw = soc_data->calc_pll("mpll", val); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_clk_data->hws[ASPEED_CLK_MPLL] = hw; + + /* SD/SDIO clock divider (TODO: There's a gate too) */ + hw = clk_hw_register_divider_table(dev, "sdio", "hpll", 0, + scu_base + ASPEED_CLK_SELECTION, 12, 3, 0, + soc_data->div_table, + &aspeed_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_clk_data->hws[ASPEED_CLK_SDIO] = hw; + + /* MAC AHB bus clock divider */ + hw = clk_hw_register_divider_table(dev, "mac", "hpll", 0, + scu_base + ASPEED_CLK_SELECTION, 16, 3, 0, + soc_data->mac_div_table, + &aspeed_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_clk_data->hws[ASPEED_CLK_MAC] = hw; + + /* LPC Host (LHCLK) clock divider */ + hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0, + scu_base + ASPEED_CLK_SELECTION, 20, 3, 0, + soc_data->div_table, + &aspeed_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_clk_data->hws[ASPEED_CLK_LHCLK] = hw; + + /* Video Engine (ECLK) mux and clock divider */ + hw = clk_hw_register_mux(dev, "eclk_mux", + eclk_parents, ARRAY_SIZE(eclk_parents), 0, + scu_base + ASPEED_CLK_SELECTION, 2, 2, + 0, &aspeed_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_clk_data->hws[ASPEED_CLK_ECLK_MUX] = hw; + hw = clk_hw_register_divider_table(dev, "eclk", "eclk_mux", 0, + scu_base + ASPEED_CLK_SELECTION, 28, 3, 0, + soc_data->eclk_div_table, + &aspeed_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_clk_data->hws[ASPEED_CLK_ECLK] = hw; + + /* P-Bus (BCLK) clock divider */ + hw = clk_hw_register_divider_table(dev, "bclk", "hpll", 0, + scu_base + ASPEED_CLK_SELECTION_2, 0, 2, 0, + soc_data->div_table, + &aspeed_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_clk_data->hws[ASPEED_CLK_BCLK] = hw; + + return 0; +}; + +static const struct of_device_id aspeed_clk_dt_ids[] = { + { .compatible = "aspeed,ast2400-scu", .data = &ast2400_data }, + { .compatible = "aspeed,ast2500-scu", .data = &ast2500_data }, + { } +}; + +static struct platform_driver aspeed_clk_driver = { + .probe = aspeed_clk_probe, + .driver = { + .name = "aspeed-clk", + .of_match_table = aspeed_clk_dt_ids, + .suppress_bind_attrs = true, + }, +}; +builtin_platform_driver(aspeed_clk_driver); + static void __init aspeed_ast2400_cc(struct regmap *map) { struct clk_hw *hw;