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[209.132.180.67]) by mx.google.com with ESMTP id b3si6675079pgr.350.2017.10.02.23.56.30; Mon, 02 Oct 2017 23:56:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=a3+ttZZc; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751207AbdJCG42 (ORCPT + 26 others); Tue, 3 Oct 2017 02:56:28 -0400 Received: from mail-pf0-f196.google.com ([209.85.192.196]:38812 "EHLO mail-pf0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750812AbdJCG40 (ORCPT ); Tue, 3 Oct 2017 02:56:26 -0400 Received: by mail-pf0-f196.google.com with SMTP id a7so8124245pfj.5; Mon, 02 Oct 2017 23:56:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=RlGlalJksVUWJPjGT5fUin70Zm3gJnxIwwKJTBvTPHM=; b=a3+ttZZcwEU0xxrILQ53Zop66x1KHnrmUR552XAbYpk0cs/fbhmBTGWqMUCSbcMfup b4gVo+ec9+Y5kJFWTGjB0PiMywvTWmr2Jo5qn4a0iVtWIq5LWaaSDfUiFb0/4nGZJdoU Z+tgNPFwgZS/jWwtFK62FF08vm1nn2E2Wz0sfeqS+nUsmB/WLE2wexXcjRGbRBLW+plJ 4wXCIpnfjAtIVCChTclTcpbtJGJBy1XwNCdQlBmcJNYW5oKEFyu1zqPp/629rGYZ1ln2 2zA2MKJVT5ih7u3LH0gUegXlvzHHT69i9qtKJb3yo3uOsun/pLiHeHsSbnb533e/d9pW mwxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=RlGlalJksVUWJPjGT5fUin70Zm3gJnxIwwKJTBvTPHM=; b=ln95DfvsPGn6phqKYzGzfV5azw5bnYLzqqT7cGaaTMtn8mSwQtfEYNQVaZ26GoTRkv BrPpydMNhAm11cJUV+WAq9xIAhn3fmtPL3exH9ZQUXq58RXaFfK5mxn+PXObmu7tFp+c Jf+rL/KSV6g8CM9/apXZTKLXucdT5MxrMPyWtwMGA/pHr22MJrk49gPhy++VBOou7sN/ 8X3NL0c3aaGbKKS3dikeuwq+SOfBVHYnAkBlqM14SupfNKpztVCEo7ZX6Wwzh+G9S7hJ CjxTjMX97CK+oJQ83CxDxf5QcF0QQ5AEpT6abrKZs2WfM0y9nv6SXmkL6CgmQnTBWh+0 bFhw== X-Gm-Message-State: AHPjjUhFD9aaTaWupoM02LpsHOOQnNCI3doh7tjwT95sJqf+0ZpNk7Ur zCI7jaLy+1AuqEAhLnCwgTk= X-Google-Smtp-Source: AOwi7QAbB/JvcPG+7ktBL0DFqneVT/Q5CKGu0Zft8klxreI6dZUQJACzRpHyW89N6cgh8wxbwujbjg== X-Received: by 10.98.62.80 with SMTP id l77mr16536193pfa.267.1507013786226; Mon, 02 Oct 2017 23:56:26 -0700 (PDT) Received: from aurora.jms.id.au ([203.0.153.9]) by smtp.gmail.com with ESMTPSA id t17sm20237368pfi.31.2017.10.02.23.56.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 02 Oct 2017 23:56:24 -0700 (PDT) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Tue, 03 Oct 2017 17:26:17 +1030 From: Joel Stanley To: Lee Jones , Michael Turquette , Stephen Boyd Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Andrew Jeffery , Benjamin Herrenschmidt , Jeremy Kerr , Rick Altherr , Ryan Chen , Arnd Bergmann Subject: [PATCH v4 2/5] clk: aspeed: Register core clocks Date: Tue, 3 Oct 2017 17:25:37 +1030 Message-Id: <20171003065540.11722-3-joel@jms.id.au> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171003065540.11722-1-joel@jms.id.au> References: <20171003065540.11722-1-joel@jms.id.au> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This registers the core clocks; those which are required to calculate the rate of the timer peripheral so the system can load a clocksource driver. Signed-off-by: Joel Stanley --- v4: - Add defines to document the BIT() macros v3: - Fix ast2400 ahb calculation - Remove incorrect 'this is wrong' comment - Separate out clkin calc to be per platform - Support 48MHz clkin on ast2400 --- drivers/clk/clk-aspeed.c | 177 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 177 insertions(+) -- 2.14.1 Reviewed-by: Andrew Jeffery diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c index a45eb351bb05..d39cf51a5114 100644 --- a/drivers/clk/clk-aspeed.c +++ b/drivers/clk/clk-aspeed.c @@ -20,7 +20,23 @@ #include +#define ASPEED_RESET_CTRL 0x04 +#define ASPEED_CLK_SELECTION 0x08 +#define ASPEED_CLK_STOP_CTRL 0x0c +#define ASPEED_MPLL_PARAM 0x20 +#define ASPEED_HPLL_PARAM 0x24 +#define AST2500_HPLL_BYPASS_EN BIT(20) +#define AST2400_HPLL_STRAPPED BIT(18) +#define AST2400_HPLL_BYPASS_EN BIT(17) +#define ASPEED_MISC_CTRL 0x2c +#define UART_DIV13_EN BIT(12) #define ASPEED_STRAP 0x70 +#define CLKIN_25MHZ_EN BIT(23) +#define AST2400_CLK_SOURCE_SEL BIT(18) +#define ASPEED_CLK_SELECTION_2 0xd8 + +/* Globally visible clocks */ +static DEFINE_SPINLOCK(aspeed_clk_lock); /* Keeps track of all clocks */ static struct clk_hw_onecell_data *aspeed_clk_data; @@ -98,6 +114,160 @@ static const struct aspeed_gate_data aspeed_gates[] __initconst = { [ASPEED_CLK_GATE_LHCCLK] = { 28, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */ }; +static const struct clk_div_table ast2400_div_table[] = { + { 0x0, 2 }, + { 0x1, 4 }, + { 0x2, 6 }, + { 0x3, 8 }, + { 0x4, 10 }, + { 0x5, 12 }, + { 0x6, 14 }, + { 0x7, 16 }, + { 0 } +}; + +static const struct clk_div_table ast2500_div_table[] = { + { 0x0, 4 }, + { 0x1, 8 }, + { 0x2, 12 }, + { 0x3, 16 }, + { 0x4, 20 }, + { 0x5, 24 }, + { 0x6, 28 }, + { 0x7, 32 }, + { 0 } +}; + +static struct clk_hw *aspeed_ast2400_calc_pll(const char *name, u32 val) +{ + unsigned int mult, div; + + if (val & AST2400_HPLL_BYPASS_EN) { + /* Pass through mode */ + mult = div = 1; + } else { + /* F = 24Mhz * (2-OD) * [(N + 2) / (D + 1)] */ + u32 n = (val >> 5) & 0x3f; + u32 od = (val >> 4) & 0x1; + u32 d = val & 0xf; + + mult = (2 - od) * (n + 2); + div = d + 1; + } + return clk_hw_register_fixed_factor(NULL, name, "clkin", 0, + mult, div); +}; + +static struct clk_hw *aspeed_ast2500_calc_pll(const char *name, u32 val) +{ + unsigned int mult, div; + + if (val & AST2500_HPLL_BYPASS_EN) { + /* Pass through mode */ + mult = div = 1; + } else { + /* F = clkin * [(M+1) / (N+1)] / (P + 1) */ + u32 p = (val >> 13) & 0x3f; + u32 m = (val >> 5) & 0xff; + u32 n = val & 0x1f; + + mult = (m + 1) / (n + 1); + div = p + 1; + } + + return clk_hw_register_fixed_factor(NULL, name, "clkin", 0, + mult, div); +} + +static void __init aspeed_ast2400_cc(struct regmap *map) +{ + struct clk_hw *hw; + u32 val, freq, div; + + /* + * CLKIN is the crystal oscillator, 24, 48 or 25MHz selected by + * strapping + */ + regmap_read(map, ASPEED_STRAP, &val); + if (val & CLKIN_25MHZ_EN) + freq = 25000000; + else if (val & AST2400_CLK_SOURCE_SEL) + freq = 48000000; + else + freq = 24000000; + hw = clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, freq); + pr_debug("clkin @%u MHz\n", freq / 1000000); + + /* + * High-speed PLL clock derived from the crystal. This the CPU clock, + * and we assume that it is enabled + */ + regmap_read(map, ASPEED_HPLL_PARAM, &val); + WARN(val & AST2400_HPLL_STRAPPED, "hpll is strapped not configured"); + aspeed_clk_data->hws[ASPEED_CLK_HPLL] = aspeed_ast2400_calc_pll("hpll", val); + + /* + * Strap bits 11:10 define the CPU/AHB clock frequency ratio (aka HCLK) + * 00: Select CPU:AHB = 1:1 + * 01: Select CPU:AHB = 2:1 + * 10: Select CPU:AHB = 4:1 + * 11: Select CPU:AHB = 3:1 + */ + regmap_read(map, ASPEED_STRAP, &val); + val = (val >> 10) & 0x3; + div = val + 1; + if (div == 3) + div = 4; + else if (div == 4) + div = 3; + hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, div); + aspeed_clk_data->hws[ASPEED_CLK_AHB] = hw; + + /* APB clock clock selection register SCU08 (aka PCLK) */ + hw = clk_hw_register_divider_table(NULL, "apb", "hpll", 0, + scu_base + ASPEED_CLK_SELECTION, 23, 3, 0, + ast2400_div_table, + &aspeed_clk_lock); + aspeed_clk_data->hws[ASPEED_CLK_APB] = hw; +} + +static void __init aspeed_ast2500_cc(struct regmap *map) +{ + struct clk_hw *hw; + u32 val, freq, div; + + /* CLKIN is the crystal oscillator, 24 or 25MHz selected by strapping */ + regmap_read(map, ASPEED_STRAP, &val); + if (val & CLKIN_25MHZ_EN) + freq = 25000000; + else + freq = 24000000; + hw = clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, freq); + pr_debug("clkin @%u MHz\n", freq / 1000000); + + /* + * High-speed PLL clock derived from the crystal. This the CPU clock, + * and we assume that it is enabled + */ + regmap_read(map, ASPEED_HPLL_PARAM, &val); + aspeed_clk_data->hws[ASPEED_CLK_HPLL] = aspeed_ast2500_calc_pll("hpll", val); + + /* Strap bits 11:9 define the AXI/AHB clock frequency ratio (aka HCLK)*/ + regmap_read(map, ASPEED_STRAP, &val); + val = (val >> 9) & 0x7; + WARN(val == 0, "strapping is zero: cannot determine ahb clock"); + div = 2 * (val + 1); + hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, div); + aspeed_clk_data->hws[ASPEED_CLK_AHB] = hw; + + /* APB clock clock selection register SCU08 (aka PCLK) */ + regmap_read(map, ASPEED_CLK_SELECTION, &val); + val = (val >> 23) & 0x7; + div = 4 * (val + 1); + hw = clk_hw_register_fixed_factor(NULL, "apb", "hpll", 0, 1, div); + aspeed_clk_data->hws[ASPEED_CLK_APB] = hw; +}; + static void __init aspeed_cc_init(struct device_node *np) { struct regmap *map; @@ -139,6 +309,13 @@ static void __init aspeed_cc_init(struct device_node *np) return; } + if (of_device_is_compatible(np, "aspeed,ast2400-scu")) + aspeed_ast2400_cc(map); + else if (of_device_is_compatible(np, "aspeed,ast2500-scu")) + aspeed_ast2500_cc(map); + else + pr_err("unknown platform, failed to add clocks\n"); + aspeed_clk_data->num = ASPEED_NUM_CLKS; ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_clk_data); if (ret)