From patchwork Thu Sep 21 04:26:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 113187 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp1564714qgf; Wed, 20 Sep 2017 21:27:51 -0700 (PDT) X-Received: by 10.84.233.65 with SMTP id k1mr4181489plt.284.1505968071659; Wed, 20 Sep 2017 21:27:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505968071; cv=none; d=google.com; s=arc-20160816; b=yMDVC+5YCbZTVitckkSpWsXbibDAvrkiArOuftxpoNmY7UeoGq6YVMr9bxeRDp/bIG 3ctMrHZV7PbQuZrrMG9Q+0gYjU9AviOVn2mKnBe5mt7twV0zTyf7j5J3AZ+QNTssAOSN qYHbB72vybFm9wIrrHRraWpeJCJSR+Ydb3abLlq3EpSmEx6oRdJB2lKa2ElckJ4W8F5z ommLgiTHNB+MKE7TpdhlLkE2Pu8ZJovr0hVHmGRaSJP2TLjCbQBHgiVYPlL8l4D22JZs mOjLpUR74d6G6UQS3SgiePNN756aOM6m4MFHS+sHKDBsEqMdyr76F/Pztqz5XTucO7Aa kPcQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=b+e7RzS2JHUR1Pqlfo1Armqkyb6M0bgr+J6rJl1yRng=; b=Aj1+8vDLMMcYsu6JvsiIiyGlvEOFjcumho3ENj8+LkR+kBTkdPqdTvV1qKPscH14Ri p0650BiUcqJO5WmMntrt3tnNdaBc041NUpWj7sjvUSLsPxq1Rkbws2EpHNVSbK/iQ6SY 2y20iuimv+xNWwae9GTNovlbJdNJxlrPqb5eeqq9nhSefpYDvWhEDMTPHSt1iKp0mKqB h+NjLu4XSzC7fMUTviSwNmKnKHqTs9F7QmbdYjiye6iVmIGL3TmiP4Yk/JLobAwMClC9 Jd0ED0sFkrbvJ+XlnM1JYqDdPv1dn450m1/bFYMGw3oPUK6kyMlLbvf6ur3rnfAPs/dw fqhA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=ag8Kmszw; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x15si421341pff.156.2017.09.20.21.27.51; Wed, 20 Sep 2017 21:27:51 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=ag8Kmszw; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751796AbdIUE1t (ORCPT + 26 others); Thu, 21 Sep 2017 00:27:49 -0400 Received: from mail-pg0-f66.google.com ([74.125.83.66]:34562 "EHLO mail-pg0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750912AbdIUE1r (ORCPT ); Thu, 21 Sep 2017 00:27:47 -0400 Received: by mail-pg0-f66.google.com with SMTP id u18so2796037pgo.1; Wed, 20 Sep 2017 21:27:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=b+e7RzS2JHUR1Pqlfo1Armqkyb6M0bgr+J6rJl1yRng=; b=ag8KmszwNGiafFBoi7LWcyblhw0lViod7hXYMeY40mxn7UIlcd3TQk5RLwkMYApuzl iO8m9l/BjrcBpxV83c8w0U4WBugQdOaoB7r3DHvgL24Ggv5OtSyI/oXuczDaEw3ypvE0 J4viI8HHia9p17jnRVdUC6HlJzAQGzayDH/mllMCp2Mpd29ZYge/682hxpC7X/5FSS+7 7qwyBdmza9cBVFuu1HL5wWL1axB14/Onrs3vp7uriSQny7piiyvpdxzpd9KQjmuHJa/l WI1mcJ4TEuPRuIZiTmZuA5liVC9F4r4W2ztU52nml8IpRb7XvTj9Da/uwmXNemJIZt94 A3wQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=b+e7RzS2JHUR1Pqlfo1Armqkyb6M0bgr+J6rJl1yRng=; b=POh7iMI9Wa38A40+/0BOnzkZA3N1R+mRCtDArd1YNxvtO/eqrpGJTBxKuoQoKdE1NT 6AoyLxOndob2jqcksFkTg9ycwHfVvXE1P9WtQW9j/NWSxtRtixRsey1pIh4uzwLu4AoX T3eDE6O23NEtN63vPdykpQOkJDlZJZuGbohAykiHLhcWFSq78NlP6l4jn2IXM9uu3Fh2 zQDxRZy66+KJgpeRUIihuhE/TUKOPaUyv0VVAOPA+rj5mODtVk6GcIe5SV7ugzF9/EcB DdLgw8BSOk9dqPKruvphqkGGmjXatBylh4STLcG/ZUrgS85odwNXQ9RNSpYWnL2KYr2/ mJbg== X-Gm-Message-State: AHPjjUgyaEy666GBbDUJlTlg8Hi89ZY0iXYrawA96a21cLQ/11fUzy1C a8YZ1u9kZlZudJaJcQiQNgE= X-Google-Smtp-Source: AOwi7QB3t5w5Z3U56cLul6J7t2v/DmBvaCPyFy7CHlgCYEqRPWA4+fSzI897XkB8KuMsuu3DCSwoNA== X-Received: by 10.98.32.139 with SMTP id m11mr4423522pfj.172.1505968066868; Wed, 20 Sep 2017 21:27:46 -0700 (PDT) Received: from aurora.jms.id.au ([203.0.153.9]) by smtp.gmail.com with ESMTPSA id 65sm584995pgh.31.2017.09.20.21.27.40 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 20 Sep 2017 21:27:45 -0700 (PDT) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Thu, 21 Sep 2017 13:57:38 +0930 From: Joel Stanley To: Lee Jones , Michael Turquette , Stephen Boyd Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Andrew Jeffery , Benjamin Herrenschmidt , Jeremy Kerr , Rick Altherr , Ryan Chen , Arnd Bergmann Subject: [PATCH v2 5/5] clk: aspeed: Add reset controller Date: Thu, 21 Sep 2017 13:56:41 +0930 Message-Id: <20170921042641.7326-6-joel@jms.id.au> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170921042641.7326-1-joel@jms.id.au> References: <20170921042641.7326-1-joel@jms.id.au> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org There are some resets that are not associated with gates. These are represented by a reset controller. Signed-off-by: Joel Stanley --- drivers/clk/clk-aspeed.c | 82 +++++++++++++++++++++++++++++++- include/dt-bindings/clock/aspeed-clock.h | 9 ++++ 2 files changed, 90 insertions(+), 1 deletion(-) -- 2.14.1 diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c index dec9db4ec47b..db97c0f9f99e 100644 --- a/drivers/clk/clk-aspeed.c +++ b/drivers/clk/clk-aspeed.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -256,6 +257,68 @@ static const struct clk_ops aspeed_clk_gate_ops = { .is_enabled = aspeed_clk_is_enabled, }; +/** + * struct aspeed_reset - Aspeed reset controller + * @map: regmap to access the containing system controller + * @rcdev: reset controller device + */ +struct aspeed_reset { + struct regmap *map; + struct reset_controller_dev rcdev; +}; + +#define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev) + +static const u8 aspeed_resets[] = { + 25, /* x-dma */ + 24, /* mctp */ + 23, /* adc */ + 22, /* jtag-master */ + 18, /* mic */ + 9, /* pwm */ + 8, /* pci-vga */ + 2, /* i2c */ + 1, /* ahb */ +}; + +static int aspeed_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct aspeed_reset *ar = to_aspeed_reset(rcdev); + u32 rst = BIT(aspeed_resets[id]); + + return regmap_update_bits(ar->map, ASPEED_RESET_CTRL, rst, 0); +} + +static int aspeed_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct aspeed_reset *ar = to_aspeed_reset(rcdev); + u32 rst = BIT(aspeed_resets[id]); + + return regmap_update_bits(ar->map, ASPEED_RESET_CTRL, rst, rst); +} + +static int aspeed_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct aspeed_reset *ar = to_aspeed_reset(rcdev); + u32 val, rst = BIT(aspeed_resets[id]); + int ret; + + ret = regmap_read(ar->map, ASPEED_RESET_CTRL, &val); + if (ret) + return ret; + + return !!(val & rst); +} + +static const struct reset_control_ops aspeed_reset_ops = { + .assert = aspeed_reset_assert, + .deassert = aspeed_reset_deassert, + .status = aspeed_reset_status, +}; + static struct clk_hw *aspeed_clk_hw_register_gate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, struct regmap *map, u8 clock_idx, u8 reset_idx, @@ -299,10 +362,11 @@ static int __init aspeed_clk_probe(struct platform_device *pdev) const struct clk_div_table *mac_div_table; const struct clk_div_table *div_table; struct device *dev = &pdev->dev; + struct aspeed_reset *ar; struct regmap *map; struct clk_hw *hw; u32 val, rate; - int i; + int i, ret; map = syscon_node_to_regmap(dev->of_node); if (IS_ERR(map)) { @@ -310,6 +374,22 @@ static int __init aspeed_clk_probe(struct platform_device *pdev) return PTR_ERR(map); } + ar = devm_kzalloc(dev, sizeof(*ar), GFP_KERNEL); + if (!ar) + return -ENOMEM; + + ar->map = map; + ar->rcdev.owner = THIS_MODULE; + ar->rcdev.nr_resets = ARRAY_SIZE(aspeed_resets); + ar->rcdev.ops = &aspeed_reset_ops; + ar->rcdev.of_node = dev->of_node; + + ret = devm_reset_controller_register(dev, &ar->rcdev); + if (ret) { + dev_err(dev, "could not register reset controller\n"); + return ret; + } + /* SoC generations share common layouts but have different divisors */ soc_data = of_device_get_match_data(&pdev->dev); div_table = soc_data->div_table; diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h index afe06b77562d..a9d552b6bbd2 100644 --- a/include/dt-bindings/clock/aspeed-clock.h +++ b/include/dt-bindings/clock/aspeed-clock.h @@ -40,4 +40,13 @@ #define ASPEED_CLK_GATE_SDCLKCLK (22 + ASPEED_CLK_GATES) #define ASPEED_CLK_GATE_LHCCLK (23 + ASPEED_CLK_GATES) +#define ASPEED_RESET_XDMA 0 +#define ASPEED_RESET_MCTP 1 +#define ASPEED_RESET_JTAG_MASTER 2 +#define ASPEED_RESET_MIC 3 +#define ASPEED_RESET_PWM 4 +#define ASPEED_RESET_PCIVGA 5 +#define ASPEED_RESET_I2C 6 +#define ASPEED_RESET_AHB 7 + #endif