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[209.132.180.67]) by mx.google.com with ESMTP id o20si413140pli.593.2017.09.20.21.27.34; Wed, 20 Sep 2017 21:27:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=TWGytX5K; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751730AbdIUE1c (ORCPT + 26 others); Thu, 21 Sep 2017 00:27:32 -0400 Received: from mail-pf0-f195.google.com ([209.85.192.195]:33240 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751692AbdIUE12 (ORCPT ); Thu, 21 Sep 2017 00:27:28 -0400 Received: by mail-pf0-f195.google.com with SMTP id h4so2030702pfk.0; Wed, 20 Sep 2017 21:27:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=71OEE59wegSaKwixxe4ovMVJpQZrOikv73NsqgYfjWM=; b=TWGytX5K0TMenYDPZO7xfjLpQrjUX10ewaVSWp9UbSahdsh8GDJ4YVgr09RvUuytJJ Wf0tTRorWmxXDcidtTCMy9WrJexxrzKjJmymMnTt+7bgh6anpwD+n1wUNjzoWHLRaDRh Gud/haISBhvTEDVHXWRwv/K2ZHS15vif9I4v8TQdYJIBApf5Xv4hQ0nKyNxALxKUF1Ce p4/F9TA90ggClVyxuD+gEPY1JZI3Ttn3plIZa/o0I0RHqEByS3kgDeuUSkqfouovcSxj Zo3mxiu06UOvnmUnMGfGmn9RVd63daygvDHTYYYRfxOpMziObAR2gABJPGjwZ9DePM4C /D/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=71OEE59wegSaKwixxe4ovMVJpQZrOikv73NsqgYfjWM=; b=r0Ll6TKkMNMsKoVVfCkUwlkP/vnIc7+zv+3Sx/U686/HLCE7qXQG6SSCWVPMhps96A WPcHJJdr07w7nLrBtdorpdHEyyXXlRDaoic3uGRShq4OFAfpL3Q72rI37YyBvilfrTwH xJCCKbZOcjvlJJKlcA9UznDCS4jiSZ6skvCABT1ojpE3mw2628YLCSeCw2yc9f+xS+gd 7JDZqkBXJe8j5Oh4v1LZryatyu2iRb3i42AzFDzCYe2QSQEKnGu3j89MUMfP+1L1Rt0K 8Jkr8RlOWbrX+Qe/MGluchtXfRIwMJUbjaRyqxh8+aRqxYMwJKZHCAeVtZN+aLNbmqQ9 OlGQ== X-Gm-Message-State: AHPjjUg2+AuyQ/jgyg/oKX24kY0mDsyjTpNu4K9L3PyiAlpO+h6JDqUS wvpF71ryRzHH4GCJCkSmqGg= X-Google-Smtp-Source: AOwi7QD1jKerE7EJrB1AHcuX/FVNWKOstKwQr8yJ3MMQSM8hnKpOnXiAsKrsIshFqDWjaotFN4A18g== X-Received: by 10.84.193.131 with SMTP id f3mr4080378pld.90.1505968047894; Wed, 20 Sep 2017 21:27:27 -0700 (PDT) Received: from aurora.jms.id.au ([203.0.153.9]) by smtp.gmail.com with ESMTPSA id v2sm558715pgo.38.2017.09.20.21.27.21 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 20 Sep 2017 21:27:26 -0700 (PDT) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Thu, 21 Sep 2017 13:57:18 +0930 From: Joel Stanley To: Lee Jones , Michael Turquette , Stephen Boyd Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Andrew Jeffery , Benjamin Herrenschmidt , Jeremy Kerr , Rick Altherr , Ryan Chen , Arnd Bergmann Subject: [PATCH v2 3/5] clk: aspeed: Add platform driver and register PLLs Date: Thu, 21 Sep 2017 13:56:39 +0930 Message-Id: <20170921042641.7326-4-joel@jms.id.au> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170921042641.7326-1-joel@jms.id.au> References: <20170921042641.7326-1-joel@jms.id.au> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This registers a platform driver to set up all of the non-core clocks. The clocks that have configurable rates are now registered. Signed-off-by: Joel Stanley --- drivers/clk/clk-aspeed.c | 129 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 129 insertions(+) -- 2.14.1 diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c index e614c61b82d2..19531798e040 100644 --- a/drivers/clk/clk-aspeed.c +++ b/drivers/clk/clk-aspeed.c @@ -14,6 +14,8 @@ #include #include #include +#include +#include #include #include #include @@ -115,6 +117,20 @@ static const struct aspeed_gate_data aspeed_gates[] __initconst = { /* 31: reserved */ }; +static const char * const eclk_parents[] = {"d1pll", "hpll", "mpll"}; + +static const struct clk_div_table ast2500_mac_div_table[] = { + { 0x0, 4 }, /* Yep, really. Aspeed confirmed this is correct */ + { 0x1, 4 }, + { 0x2, 6 }, + { 0x3, 8 }, + { 0x4, 10 }, + { 0x5, 12 }, + { 0x6, 14 }, + { 0x7, 16 }, + { 0 } +}; + static const struct clk_div_table ast2400_div_table[] = { { 0x0, 2 }, { 0x1, 4 }, @@ -139,6 +155,21 @@ static const struct clk_div_table ast2500_div_table[] = { { 0 } }; +struct aspeed_clk_soc_data { + const struct clk_div_table *div_table; + const struct clk_div_table *mac_div_table; +}; + +static const struct aspeed_clk_soc_data ast2500_data = { + .div_table = ast2500_div_table, + .mac_div_table = ast2500_mac_div_table, +}; + +static const struct aspeed_clk_soc_data ast2400_data = { + .div_table = ast2400_div_table, + .mac_div_table = ast2400_div_table, +}; + static struct clk_hw *aspeed_calc_pll(const char *name, u32 val) { unsigned int mult, div; @@ -160,6 +191,104 @@ static struct clk_hw *aspeed_calc_pll(const char *name, u32 val) mult, div); } +static int __init aspeed_clk_probe(struct platform_device *pdev) +{ + const struct aspeed_clk_soc_data *soc_data; + const struct clk_div_table *mac_div_table; + const struct clk_div_table *div_table; + struct device *dev = &pdev->dev; + struct regmap *map; + struct clk_hw *hw; + u32 val, rate; + + map = syscon_node_to_regmap(dev->of_node); + if (IS_ERR(map)) { + dev_err(dev, "no syscon regmap\n"); + return PTR_ERR(map); + } + + /* SoC generations share common layouts but have different divisors */ + soc_data = of_device_get_match_data(&pdev->dev); + div_table = soc_data->div_table; + mac_div_table = soc_data->mac_div_table; + + /* UART clock div13 setting */ + regmap_read(map, ASPEED_MISC_CTRL, &val); + if (val & BIT(12)) + rate = 24000000 / 13; + else + rate = 24000000; + /* TODO: Find the parent data for the uart clock */ + hw = clk_hw_register_fixed_rate(NULL, "uart", NULL, 0, rate); + aspeed_clk_data->hws[ASPEED_CLK_UART] = hw; + + /* + * Memory controller (M-PLL) PLL. This clock is configured by the + * bootloader, and is exposed to Linux as a read-only clock rate. + */ + regmap_read(map, ASPEED_MPLL_PARAM, &val); + aspeed_clk_data->hws[ASPEED_CLK_MPLL] = aspeed_calc_pll("mpll", val); + + /* SD/SDIO clock divider (TODO: There's a gate too) */ + hw = clk_hw_register_divider_table(NULL, "sdio", "hpll", 0, + scu_base + ASPEED_CLK_SELECTION, 12, 3, 0, + div_table, + &aspeed_clk_lock); + aspeed_clk_data->hws[ASPEED_CLK_SDIO] = hw; + + /* MAC AHB bus clock divider */ + hw = clk_hw_register_divider_table(NULL, "mac", "hpll", 0, + scu_base + ASPEED_CLK_SELECTION, 16, 3, 0, + mac_div_table, + &aspeed_clk_lock); + aspeed_clk_data->hws[ASPEED_CLK_MAC] = hw; + + /* LPC Host (LHCLK) clock divider */ + hw = clk_hw_register_divider_table(NULL, "lhclk", "hpll", 0, + scu_base + ASPEED_CLK_SELECTION, 20, 3, 0, + div_table, + &aspeed_clk_lock); + aspeed_clk_data->hws[ASPEED_CLK_LHCLK] = hw; + + /* Video Engine (ECLK) mux and clock divider */ + hw = clk_hw_register_mux(NULL, "eclk_mux", + eclk_parents, ARRAY_SIZE(eclk_parents), 0, + scu_base + ASPEED_CLK_SELECTION, 2, 2, + 0, &aspeed_clk_lock); + aspeed_clk_data->hws[ASPEED_CLK_ECLK_MUX] = hw; + hw = clk_hw_register_divider_table(NULL, "eclk", "eclk_mux", 0, + scu_base + ASPEED_CLK_SELECTION, 20, 3, 0, + div_table, + &aspeed_clk_lock); + aspeed_clk_data->hws[ASPEED_CLK_ECLK] = hw; + + /* P-Bus (BCLK) clock divider */ + hw = clk_hw_register_divider_table(NULL, "bclk", "hpll", 0, + scu_base + ASPEED_CLK_SELECTION, 0, 2, 0, + div_table, + &aspeed_clk_lock); + aspeed_clk_data->hws[ASPEED_CLK_BCLK] = hw; + + return 0; +}; + +static const struct of_device_id aspeed_clk_dt_ids[] = { + { .compatible = "aspeed,ast2400-scu", .data = &ast2400_data }, + { .compatible = "aspeed,ast2500-scu", .data = &ast2500_data }, + { }, +}; + +static struct platform_driver aspeed_clk_driver = { + .probe = aspeed_clk_probe, + .driver = { + .name = "aspeed-clk", + .of_match_table = aspeed_clk_dt_ids, + .suppress_bind_attrs = true, + }, +}; +builtin_platform_driver(aspeed_clk_driver); + + static void __init aspeed_ast2400_cc(struct regmap *map) { struct clk_hw *hw;