From patchwork Thu Sep 21 04:26:38 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 113184 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp1564498qgf; Wed, 20 Sep 2017 21:27:28 -0700 (PDT) X-Received: by 10.98.68.82 with SMTP id r79mr4444051pfa.184.1505968048068; Wed, 20 Sep 2017 21:27:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505968048; cv=none; d=google.com; s=arc-20160816; b=i9kUmRycAtWZrkw55FjSVP+vdNL8xVceAfsJpb4MSQdfM6PCLCkiGHJQ+7f6A/ObiN UdLqHSdTT0/p5gTcRoO5qL6o+nCpztCzancnknMU3FZT41ZMiiyzeVDuNEHPn2uWr7J8 0m/sBJGwI2c5QMSt7iiyEa7UP6sR1zmC6rDvt/7wkAJFVlieQ1fno+aP6AstPdtYz8lk L4/H6FBop0WGMSXtsBEukvYJjl8wjIkdQCzTelE8B3FAaGZXAg20A27PRUAkjJveAxKf d8dDUiYD4RygsCMhvoVj3EEQq4nn9Yjeo7cATrPSTrYj/xw1qHu6DLIZms12B2SfeTaj 70OA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=JetSevOtzdWEejiJr20GOvgN21Zq1cep7LT+4+3o+XM=; b=nOAS8NFjz6elAP4ZadWC6rLmJUpie66qeffz6fO9kvVVMNKBa3UV3TxUFlFx5GKSh8 jUeAzFQgP92/nMA0DWCiNLSESD4sdKQrkiGR9QZr4OK25sK564Va1PHnR8QNGdjJ16VE BAq/mbcbEWvZSkqbz4UDUQIG6QW+ze4gFdTzLZ2wqx0KGMfPe4PvcgiFLbhGjrElJ9mb E/UsC37/dCIrE2K5NAmGfkvgn7EpqG04B6/p1uRETyv0UNl6W4n2h60oP8QbLiqWk85h GOatha623/e58b8YDImVo8VnyANGs1Pkdpaldeg6CwrUYMWpPBOfcQULm1OpmHJahDo1 Db6w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=Qa/1bEae; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 5si410614plx.272.2017.09.20.21.27.27; Wed, 20 Sep 2017 21:27:28 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=Qa/1bEae; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751681AbdIUE1V (ORCPT + 26 others); Thu, 21 Sep 2017 00:27:21 -0400 Received: from mail-pf0-f194.google.com ([209.85.192.194]:35762 "EHLO mail-pf0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751635AbdIUE1S (ORCPT ); Thu, 21 Sep 2017 00:27:18 -0400 Received: by mail-pf0-f194.google.com with SMTP id i23so2021517pfi.2; Wed, 20 Sep 2017 21:27:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=JetSevOtzdWEejiJr20GOvgN21Zq1cep7LT+4+3o+XM=; b=Qa/1bEaetZlSC3q63lSdmLuwFvqpaRba7mT8Tj0fm6gwrumM9FkmSSGUVjJOWqPc9X oSgM/UOjqbTgR9YKx9OoD4VpqTkEPfpzMqXG4sp2M71TgnWfaFulouDpixwVkaiEXc5u ikjaW4YobByQQfdLGH95zhrh1SJuYWYVqjx97Sw8gIOxKynkJy8upadf49l6UoWKQAZs dpzCvcDz5fjvBtO0w4/1Bj6/gcblHoO7v1nqQGPzP6JGJXRykD3a6PS12vzqWL6UGd+O bCipIJlhM9KK4rH/FPcyZ7M56vADtrfpMqw/8/bXVFFEmcaHY4Er9KgYo8p1C0EvUy8U jO9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=JetSevOtzdWEejiJr20GOvgN21Zq1cep7LT+4+3o+XM=; b=DUYZuWdi50KDJFM6t80JeyKTr/492KB2PRRH4jW3Eh8jYk7CCZLJKZGjcBvgQZFEAt N1tN6pyhXpHVO2GQsmyAxbWp/NeA6gJMq8zT5GFA4Hfckj1VvIX0DeQ5gg030yWjNTxB A8uLfq8EYlOEocMH+tuiy9JHqir27A2IUBCbg8nneC/9zZ2Yko0h62oPbgaqc9U0AZIt 5Pq1RYeehifTtiSCSDVcbrsYPuC8qZVrPfA2hkC5NFkMTwmpv7x9hlMCUtM/sOnI+/3b kXOjn6ZIjZHg/BYDfzOyute8Tmi9UyanXXYhdH6gvPBKk4Bxp/ik8thdvQ20eKGH6Pgv GWGA== X-Gm-Message-State: AHPjjUgh3SMko9+TuFFGvxVjjxw8PLsTWTTxuBkkSgm2BilM+h6Na2Po d1iB0NyrOaOdZqydid4aRYU= X-Google-Smtp-Source: AOwi7QA3ckqtQnj8Ue7M+tQJ+TzuE+YFNqArnGPil/ezqmh/fr0E2JtpPEfq5mAUqCKiMysDG4lOAg== X-Received: by 10.84.131.105 with SMTP id 96mr4306064pld.229.1505968037841; Wed, 20 Sep 2017 21:27:17 -0700 (PDT) Received: from aurora.jms.id.au ([203.0.153.9]) by smtp.gmail.com with ESMTPSA id v71sm676017pfa.45.2017.09.20.21.27.11 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 20 Sep 2017 21:27:16 -0700 (PDT) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Thu, 21 Sep 2017 13:57:08 +0930 From: Joel Stanley To: Lee Jones , Michael Turquette , Stephen Boyd Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Andrew Jeffery , Benjamin Herrenschmidt , Jeremy Kerr , Rick Altherr , Ryan Chen , Arnd Bergmann Subject: [PATCH v2 2/5] clk: aspeed: Register core clocks Date: Thu, 21 Sep 2017 13:56:38 +0930 Message-Id: <20170921042641.7326-3-joel@jms.id.au> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170921042641.7326-1-joel@jms.id.au> References: <20170921042641.7326-1-joel@jms.id.au> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This registers the core clocks; those which are required to calculate the rate of the timer periperhal so the system can load a clocksource driver. Signed-off-by: Joel Stanley --- drivers/clk/clk-aspeed.c | 152 ++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 149 insertions(+), 3 deletions(-) -- 2.14.1 diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c index 824c54767009..e614c61b82d2 100644 --- a/drivers/clk/clk-aspeed.c +++ b/drivers/clk/clk-aspeed.c @@ -11,12 +11,12 @@ #define pr_fmt(fmt) "clk-aspeed: " fmt -#include -#include #include +#include +#include #include +#include #include -#include #include @@ -28,6 +28,9 @@ #define ASPEED_MISC_CTRL 0x2c #define ASPEED_STRAP 0x70 +/* Globally visible clocks */ +static DEFINE_SPINLOCK(aspeed_clk_lock); + /* Keeps track of all clocks */ static struct clk_hw_onecell_data *aspeed_clk_data; @@ -112,9 +115,137 @@ static const struct aspeed_gate_data aspeed_gates[] __initconst = { /* 31: reserved */ }; +static const struct clk_div_table ast2400_div_table[] = { + { 0x0, 2 }, + { 0x1, 4 }, + { 0x2, 6 }, + { 0x3, 8 }, + { 0x4, 10 }, + { 0x5, 12 }, + { 0x6, 14 }, + { 0x7, 16 }, + { 0 } +}; + +static const struct clk_div_table ast2500_div_table[] = { + { 0x0, 4 }, + { 0x1, 8 }, + { 0x2, 12 }, + { 0x3, 16 }, + { 0x4, 20 }, + { 0x5, 24 }, + { 0x6, 28 }, + { 0x7, 32 }, + { 0 } +}; + +static struct clk_hw *aspeed_calc_pll(const char *name, u32 val) +{ + unsigned int mult, div; + + if (val & BIT(20)) { + /* Pass through mode */ + mult = div = 1; + } else { + /* F = clkin * [(M+1) / (N+1)] / (P + 1) */ + u32 p = (val >> 13) & 0x3f; + u32 m = (val >> 5) & 0xff; + u32 n = val & 0x1f; + + mult = (m + 1) / (n + 1); + div = p + 1; + } + + return clk_hw_register_fixed_factor(NULL, name, "clkin", 0, + mult, div); +} + +static void __init aspeed_ast2400_cc(struct regmap *map) +{ + struct clk_hw *hw; + u32 val, div, mult; + + /* + * High-speed PLL clock derived from the crystal. This the CPU clock, + * and we assume that it is enabled + */ + regmap_read(map, ASPEED_HPLL_PARAM, &val); + WARN(val & BIT(18), "clock is strapped not configured"); + if (val & BIT(17)) { + /* Pass through mode */ + mult = div = 1; + } else { + /* F = 24Mhz * (2-OD) * [(N + 2) / (D + 1)] */ + u32 n = (val >> 5) & 0x3f; + u32 od = (val >> 4) & 0x1; + u32 d = val & 0xf; + + mult = (2 - od) * (n + 2); + div = d + 1; + } + hw = clk_hw_register_fixed_factor(NULL, "hpll", "clkin", 0, mult, div); + aspeed_clk_data->hws[ASPEED_CLK_HPLL] = hw; + + /* + * Strap bits 11:10 define the CPU/AHB clock frequency ratio (aka HCLK) + * 00: Select CPU:AHB = 1:1 + * 01: Select CPU:AHB = 2:1 + * 10: Select CPU:AHB = 4:1 + * 11: Select CPU:AHB = 3:1 + */ + regmap_read(map, ASPEED_STRAP, &val); + val = (val >> 10) & 0x3; + div = val + 1; + if (div == 2) + div = 3; + else if (div == 3) + div = 2; + hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, div); + aspeed_clk_data->hws[ASPEED_CLK_AHB] = hw; + + /* APB clock clock selection register SCU08 (aka PCLK) */ + hw = clk_hw_register_divider_table(NULL, "apb", "hpll", 0, + scu_base + ASPEED_CLK_SELECTION, 23, 3, 0, + ast2400_div_table, + &aspeed_clk_lock); + aspeed_clk_data->hws[ASPEED_CLK_APB] = hw; +} + +static void __init aspeed_ast2500_cc(struct regmap *map) +{ + struct clk_hw *hw; + u32 val, div; + + /* + * High-speed PLL clock derived from the crystal. This the CPU clock, + * and we assume that it is enabled + */ + regmap_read(map, ASPEED_HPLL_PARAM, &val); + aspeed_clk_data->hws[ASPEED_CLK_HPLL] = aspeed_calc_pll("hpll", val); + + /* Strap bits 11:9 define the AXI/AHB clock frequency ratio (aka HCLK)*/ + regmap_read(map, ASPEED_STRAP, &val); + val = (val >> 9) & 0x7; + WARN_ON(val == 0); + div = 2 * (val + 1); + hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, div); + aspeed_clk_data->hws[ASPEED_CLK_AHB] = hw; + + /* APB clock clock selection register SCU08 (aka PCLK) */ + /* TODO: this is wrong! */ + regmap_read(map, ASPEED_CLK_SELECTION, &val); + val = (val >> 23) & 0x7; + div = 4 * (val + 1); + hw = clk_hw_register_fixed_factor(NULL, "apb", "hpll", 0, 1, div); + aspeed_clk_data->hws[ASPEED_CLK_APB] = hw; +}; + + static void __init aspeed_cc_init(struct device_node *np) { struct regmap *map; + unsigned long freq; + struct clk_hw *hw; u32 val; int ret; int i; @@ -153,6 +284,21 @@ static void __init aspeed_cc_init(struct device_node *np) return; } + /* CLKIN is the crystal oscillator, 24 or 25MHz selected by strapping */ + if (val & BIT(23)) + freq = 25000000; + else + freq = 24000000; + hw = clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, freq); + pr_debug("clkin @%lu MHz\n", freq / 1000000); + + if (of_device_is_compatible(np, "aspeed,ast2400-scu")) + aspeed_ast2400_cc(map); + else if (of_device_is_compatible(np, "aspeed,ast2500-scu")) + aspeed_ast2500_cc(map); + else + pr_err("unknown platform, failed to add clocks\n"); + aspeed_clk_data->num = ASPEED_NUM_CLKS; ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_clk_data); if (ret)