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[209.132.180.67]) by mx.google.com with ESMTP id s11si1343664plj.810.2017.09.20.06.41.39; Wed, 20 Sep 2017 06:41:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=QRPa5vk3; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751889AbdITNlh (ORCPT + 26 others); Wed, 20 Sep 2017 09:41:37 -0400 Received: from mail-wr0-f178.google.com ([209.85.128.178]:48281 "EHLO mail-wr0-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751378AbdITNji (ORCPT ); Wed, 20 Sep 2017 09:39:38 -0400 Received: by mail-wr0-f178.google.com with SMTP id 108so2204949wra.5 for ; Wed, 20 Sep 2017 06:39:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4pL8lYlIG0VE/UHKe/eSABGAGTxykr6LtJmjM1gqqR8=; b=QRPa5vk39Yg3zvU1FNnH0wA0BvsI8ltaFPVCPuih5eCTmN20afYcx4RfJSkleXH72Y aynRVdSPsExsxDR8J96j9Z3hpXRRLs5Wocu63ZfwaO60tF+aj88WHIVDLdE5jM6uJGyG YICgOTV8d6n672z+yNcK1tZqMyLsIdmUsFZkRh6BdX9Os742phc1F2Qly6n19M6u7xa3 1EXs6hFfKA6qP9WzlnZQbZ6oWhaiZsjUIw4xGYJEedwZOLhYVnQxjsnTfWKfA/sG1yQB i4ybmYS+mx53O7v04nZTdZUlw16YH6iJ9v2OqDjGyow7WJIOYzLeNbZpMovzzGAzvuw1 NFFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4pL8lYlIG0VE/UHKe/eSABGAGTxykr6LtJmjM1gqqR8=; b=ImBmtvSloN6P9xfCLq8kUI9ASzaJl/05T50kVrLDVEeDDar4ayPs/5pZcNnRo7+6UD HCNqOnVDS1h3sp8TxTwEoW+Phw3WNHgzPEPIk0uQgVW3VOrpM+WpAJ1457Xcw3o64PV0 62ZXL92CuWFdtH2H/PVVMLHXCsbPVd9bjzoQrDo4SgIlL06YpHvTl9185AWGJXGi2TZT DXyZ5TRRPrDazvyrxG+DyvOgKZ1jtJCeDdjjrlLpFldx5K9xHZ7bagjDvV1QcoJyi7KU 3lvX5sJCxfOJUSlAmbqQfvKV781J86SL4s0p6hIE0T+zcdOtS2LO/92lLCsuXhe39TkS ZVxA== X-Gm-Message-State: AHPjjUingJ8fYPAq34BEOT7RRPtxKsXM1b2pdmPKWbNUnzD1RNHysZx1 1YjVtGQ8e8FGZPzeYyy3AK0l1w== X-Google-Smtp-Source: AOwi7QDEwdBYoou/Mn0vbwv5Lw+reKBdniHzwkuTjIHX3Ce75Lpn7Rfi/A/g841MS8LgSoQdIKjuEA== X-Received: by 10.223.167.79 with SMTP id e15mr4901433wrd.92.1505914776795; Wed, 20 Sep 2017 06:39:36 -0700 (PDT) Received: from localhost.localdomain ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id a39sm1938888wrc.48.2017.09.20.06.39.35 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 20 Sep 2017 06:39:36 -0700 (PDT) From: Jerome Brunet To: Linus Walleij , Kevin Hilman , Carlo Caione Cc: Jerome Brunet , linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Martin Blumenstingl Subject: [PATCH 1/8] pinctrl: meson: remove offset from pinctrl Date: Wed, 20 Sep 2017 15:39:20 +0200 Message-Id: <20170920133927.17390-2-jbrunet@baylibre.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170920133927.17390-1-jbrunet@baylibre.com> References: <20170920133927.17390-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Offset on meson pinctrl and gpios is something that was carried from the vendor driver, where there is a weird link between the 2 controllers. Since these 2 controllers are independent, this offset adds an unnecessary complexity. This patch remove this manually set offset and rely on pinctrl to figure out the gpio base offset Tested-by: Martin Blumenstingl Signed-off-by: Jerome Brunet --- drivers/pinctrl/meson/pinctrl-meson.c | 18 +++--------------- drivers/pinctrl/meson/pinctrl-meson.h | 8 +++----- 2 files changed, 6 insertions(+), 20 deletions(-) -- 2.13.5 diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c index 66ed70c12733..247208150b19 100644 --- a/drivers/pinctrl/meson/pinctrl-meson.c +++ b/drivers/pinctrl/meson/pinctrl-meson.c @@ -410,18 +410,6 @@ static const struct pinconf_ops meson_pinconf_ops = { .is_generic = true, }; -static int meson_gpio_request(struct gpio_chip *chip, unsigned gpio) -{ - return pinctrl_request_gpio(chip->base + gpio); -} - -static void meson_gpio_free(struct gpio_chip *chip, unsigned gpio) -{ - struct meson_pinctrl *pc = gpiochip_get_data(chip); - - pinctrl_free_gpio(pc->data->pin_base + gpio); -} - static int meson_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) { struct meson_pinctrl *pc = gpiochip_get_data(chip); @@ -539,13 +527,13 @@ static int meson_gpiolib_register(struct meson_pinctrl *pc) pc->chip.label = pc->data->name; pc->chip.parent = pc->dev; - pc->chip.request = meson_gpio_request; - pc->chip.free = meson_gpio_free; + pc->chip.request = gpiochip_generic_request; + pc->chip.free = gpiochip_generic_free; pc->chip.direction_input = meson_gpio_direction_input; pc->chip.direction_output = meson_gpio_direction_output; pc->chip.get = meson_gpio_get; pc->chip.set = meson_gpio_set; - pc->chip.base = pc->data->pin_base; + pc->chip.base = -1; pc->chip.ngpio = pc->data->num_pins; pc->chip.can_sleep = false; pc->chip.of_node = pc->of_node; diff --git a/drivers/pinctrl/meson/pinctrl-meson.h b/drivers/pinctrl/meson/pinctrl-meson.h index 890f296f5840..227b72a60c22 100644 --- a/drivers/pinctrl/meson/pinctrl-meson.h +++ b/drivers/pinctrl/meson/pinctrl-meson.h @@ -124,8 +124,6 @@ struct meson_pinctrl { struct device_node *of_node; }; -#define PIN(x, b) (b + x) - #define GROUP(grp, r, b) \ { \ .name = #grp, \ @@ -135,10 +133,10 @@ struct meson_pinctrl { .bit = b, \ } -#define GPIO_GROUP(gpio, b) \ +#define GPIO_GROUP(gpio) \ { \ .name = #gpio, \ - .pins = (const unsigned int[]){ PIN(gpio, b) }, \ + .pins = (const unsigned int[]){ gpio }, \ .num_pins = 1, \ .is_gpio = true, \ } @@ -166,7 +164,7 @@ struct meson_pinctrl { }, \ } -#define MESON_PIN(x, b) PINCTRL_PIN(PIN(x, b), #x) +#define MESON_PIN(x) PINCTRL_PIN(x, #x) extern struct meson_pinctrl_data meson8_cbus_pinctrl_data; extern struct meson_pinctrl_data meson8_aobus_pinctrl_data;