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[209.132.180.67]) by mx.google.com with ESMTP id g192si3623932pgc.466.2017.08.18.07.59.17; Fri, 18 Aug 2017 07:59:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=r6qFQsvN; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752587AbdHRO7P (ORCPT + 26 others); Fri, 18 Aug 2017 10:59:15 -0400 Received: from lelnx194.ext.ti.com ([198.47.27.80]:10179 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751849AbdHRO7L (ORCPT ); Fri, 18 Aug 2017 10:59:11 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v7IEx707002645; Fri, 18 Aug 2017 09:59:07 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1503068347; bh=8AYrMd9NMuxNtI/bH494xUh5tVx9P1GM7evpox9snus=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=r6qFQsvNw/B3hm/WkjP58CdXzuERI6lORKEtp9ClQzDMedQ+Y8XbljaJ96bjJPirm UK8MDn52lAKyT6yzNdPS0Q+377OMtzL03ZIfcOmexmj7JwbulrZnnbLFOsnvUVm48b ySLWJEWk++1ft+/zqLPEG5WAr5D6gspVUZ6hQ8+Q= Received: from DFLE106.ent.ti.com (dfle106.ent.ti.com [10.64.6.27]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7IEx73C012761; Fri, 18 Aug 2017 09:59:07 -0500 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Fri, 18 Aug 2017 09:59:06 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Fri, 18 Aug 2017 09:59:07 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7IEwKkD023721; Fri, 18 Aug 2017 09:59:04 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas CC: Joao Pinto , Arnd Bergmann , , , , , , Subject: [PATCH 15/18] misc: pci_endpoint_test: Add support to not enable MSI interrupts Date: Fri, 18 Aug 2017 20:28:07 +0530 Message-ID: <20170818145810.17649-16-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170818145810.17649-1-kishon@ti.com> References: <20170818145810.17649-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Some platforms like TI's K2G have a restriction that the host side buffer address should be aligned to either 1MB/2MB/4MB or 8MB addresses depending on how it is configured in the endpoint (Ref: 11.14.4.9.1 Outbound Address Translation in K2G TRM SPRUHY8F January 2016 – Revised May 2017). This restriction also applies to the MSI addresses provided by the RC. However it's not possible for the RC to know about this restriction and it may not provide 1MB/2MB/4MB or 8MB aligned address. So MSI interrupts should be disabled even if the K2G EP has MSI capabiltiy register. Add support to not enable MSI interrupts in pci_endpoint_test driver so that it can be used to test K2G EP. Signed-off-by: Kishon Vijay Abraham I --- drivers/misc/pci_endpoint_test.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) -- 2.11.0 diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c index 5f6bd23ab657..5cbb25cf276c 100644 --- a/drivers/misc/pci_endpoint_test.c +++ b/drivers/misc/pci_endpoint_test.c @@ -97,6 +97,7 @@ struct pci_endpoint_test { struct pci_endpoint_test_data { enum pci_barno test_reg_bar; size_t alignment; + bool no_msi; }; static int bar_size[] = { 512, 512, 1024, 16384, 131072, 1048576 }; @@ -449,8 +450,9 @@ static int pci_endpoint_test_probe(struct pci_dev *pdev, { int i; int err; - int irq; + int irq = 0; int id; + bool no_msi = false; char name[20]; enum pci_barno bar; void __iomem *base; @@ -475,6 +477,7 @@ static int pci_endpoint_test_probe(struct pci_dev *pdev, if (data) { test_reg_bar = data->test_reg_bar; test->alignment = data->alignment; + no_msi = data->no_msi; } init_completion(&test->irq_raised); @@ -494,9 +497,11 @@ static int pci_endpoint_test_probe(struct pci_dev *pdev, pci_set_master(pdev); - irq = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI); - if (irq < 0) - dev_err(dev, "failed to get MSI interrupts\n"); + if (!no_msi) { + irq = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI); + if (irq < 0) + dev_err(dev, "failed to get MSI interrupts\n"); + } err = devm_request_irq(dev, pdev->irq, pci_endpoint_test_irqhandler, IRQF_SHARED, DRV_MODULE_NAME, test);