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[209.132.180.67]) by mx.google.com with ESMTP id e190si3735449pfa.691.2017.08.18.08.01.40; Fri, 18 Aug 2017 08:01:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=exzUB8q+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752466AbdHRO7D (ORCPT + 26 others); Fri, 18 Aug 2017 10:59:03 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:25723 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752115AbdHRO7A (ORCPT ); Fri, 18 Aug 2017 10:59:00 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v7IEwtBC013939; Fri, 18 Aug 2017 09:58:55 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1503068335; bh=szPdfEMR28SE0YiKjXg/GN9NSnBS6QKKOM2MFGAN9qg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=exzUB8q+H95N/FgWTTeVKV3KwqbgKFWU1ALxDvOpVGSSdBy6Lc76q7+ST/0vDuZ4L 4R2P+3ep5FG2H+PDpZi7YrLoyIQNYYlNLtZZDxRQtgx0e9rqMZJdoruNjPxTgDNPSj 4MQs5214w2oGQpCvDAGly4SapXnVcsv5fUSlNGeI= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7IEwtPA003044; Fri, 18 Aug 2017 09:58:55 -0500 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Fri, 18 Aug 2017 09:58:55 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Fri, 18 Aug 2017 09:58:55 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7IEwKk9023721; Fri, 18 Aug 2017 09:58:52 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas CC: Joao Pinto , Arnd Bergmann , , , , , , Subject: [PATCH 11/18] PCI: dwc: dra7xx: Reset all BARs during initialization Date: Fri, 18 Aug 2017 20:28:03 +0530 Message-ID: <20170818145810.17649-12-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170818145810.17649-1-kishon@ti.com> References: <20170818145810.17649-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org dra7xx has all base address registers (BAR) enabled by default. Reset all BARs during initialization and so that BARs are enabled only if they are actually used. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/dwc/pci-dra7xx.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) -- 2.11.0 diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c index f2fc5f47064e..ee61f833b62c 100644 --- a/drivers/pci/dwc/pci-dra7xx.c +++ b/drivers/pci/dwc/pci-dra7xx.c @@ -335,10 +335,23 @@ static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg) return IRQ_HANDLED; } +static void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar) +{ + u32 reg; + + reg = PCI_BASE_ADDRESS_0 + (4 * bar); + dw_pcie_writel_dbi2(pci, reg, 0x0); + dw_pcie_writel_dbi(pci, reg, 0x0); +} + static void dra7xx_pcie_ep_init(struct dw_pcie_ep *ep) { struct dw_pcie *pci = to_dw_pcie_from_ep(ep); struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); + enum pci_barno bar; + + for (bar = BAR_0; bar <= BAR_5; bar++) + dw_pcie_ep_reset_bar(pci, bar); dra7xx_pcie_enable_wrapper_interrupts(dra7xx); }