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[209.132.180.67]) by mx.google.com with ESMTP id d3si2132581pln.808.2017.08.17.04.21.19; Thu, 17 Aug 2017 04:21:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752085AbdHQLUu (ORCPT + 26 others); Thu, 17 Aug 2017 07:20:50 -0400 Received: from mx2.suse.de ([195.135.220.15]:49954 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751090AbdHQLUp (ORCPT ); Thu, 17 Aug 2017 07:20:45 -0400 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay1.suse.de (charybdis-ext.suse.de [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id 0C503AABA; Thu, 17 Aug 2017 11:20:44 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Roc He , =?utf-8?b?6JKL?= =?utf-8?b?5Li955C0?= , =?utf-8?q?Andreas_F=C3=A4rber?= , Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , devicetree@vger.kernel.org Subject: [RFC 2/4] arm64: dts: realtek: Add clock nodes for RTD1295 Date: Thu, 17 Aug 2017 13:20:23 +0200 Message-Id: <20170817112026.24062-3-afaerber@suse.de> X-Mailer: git-send-email 2.12.3 In-Reply-To: <20170817112026.24062-1-afaerber@suse.de> References: <20170817112026.24062-1-afaerber@suse.de> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add 27 MHz oscillator and two clock controller nodes. Signed-off-by: Andreas Färber --- arch/arm64/boot/dts/realtek/rtd1295.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) -- 2.12.3 diff --git a/arch/arm64/boot/dts/realtek/rtd1295.dtsi b/arch/arm64/boot/dts/realtek/rtd1295.dtsi index 77063e984db9..078a11506876 100644 --- a/arch/arm64/boot/dts/realtek/rtd1295.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd1295.dtsi @@ -81,6 +81,13 @@ (GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>; }; + osc27M: osc { + compatible = "fixed-clock"; + clock-frequency = <27000000>; + #clock-cells = <0>; + clock-output-names = "osc27M"; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -88,6 +95,13 @@ /* Exclude up to 2 GiB of RAM */ ranges = <0x80000000 0x80000000 0x80000000>; + clkc: clock-controller@98000000 { + compatible = "realtek,rtd1295-clk"; + reg = <0x98000000 0x1000>; + clocks = <&osc27M>; + #clock-cells = <1>; + }; + reset1: reset-controller@98000000 { compatible = "realtek,rtd1295-reset"; reg = <0x98000000 0x4>; @@ -112,6 +126,13 @@ #reset-cells = <1>; }; + iso_clkc: clock-controller@98007000 { + compatible = "realtek,rtd1295-iso-clk"; + reg = <0x98007000 0x100>; + clocks = <&osc27M>; + #clock-cells = <1>; + }; + iso_irq_mux: interrupt-controller@98007000 { compatible = "realtek,rtd1295-iso-irq-mux"; reg = <0x98007000 0x100>;