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[209.132.180.67]) by mx.google.com with ESMTP id j22si2089251pli.981.2017.08.17.04.21.05; Thu, 17 Aug 2017 04:21:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752229AbdHQLUv (ORCPT + 26 others); Thu, 17 Aug 2017 07:20:51 -0400 Received: from mx2.suse.de ([195.135.220.15]:49948 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751076AbdHQLUq (ORCPT ); Thu, 17 Aug 2017 07:20:46 -0400 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (charybdis-ext.suse.de [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id 0C13DAAB6; Thu, 17 Aug 2017 11:20:44 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Roc He , =?utf-8?b?6JKL?= =?utf-8?b?5Li955C0?= , =?utf-8?q?Andreas_F=C3=A4rber?= , Rob Herring , Mark Rutland , devicetree@vger.kernel.org Subject: [RFC 1/4] dt-bindings: clock: Add Realtek RTD1295 Date: Thu, 17 Aug 2017 13:20:22 +0200 Message-Id: <20170817112026.24062-2-afaerber@suse.de> X-Mailer: git-send-email 2.12.3 In-Reply-To: <20170817112026.24062-1-afaerber@suse.de> References: <20170817112026.24062-1-afaerber@suse.de> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Naming inspired from Zidoo X9S Device Tree and clk_summary. Signed-off-by: Andreas Färber --- .../devicetree/bindings/clock/realtek,rtd129x.txt | 20 +++++ include/dt-bindings/clock/realtek,rtd1295.h | 99 ++++++++++++++++++++++ 2 files changed, 119 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/realtek,rtd129x.txt create mode 100644 include/dt-bindings/clock/realtek,rtd1295.h -- 2.12.3 diff --git a/Documentation/devicetree/bindings/clock/realtek,rtd129x.txt b/Documentation/devicetree/bindings/clock/realtek,rtd129x.txt new file mode 100644 index 000000000000..b55da39faf58 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/realtek,rtd129x.txt @@ -0,0 +1,20 @@ +Realtek RTD129x clock controllers +================================= + +Requires properties: +- compatible : Should be one of the following: + - "realtek,rtd1295-clk" + - "realtek,rtd1295-iso-clk" +- reg : Specifies physical base address and size +- clocks : Specifies the oscillator node +- #clock-cells : Shall be 1 + + +Example: + + clock-controller@98000000 { + compatible = "realtek,rtd1295-clk"; + reg = <0x98000000 0x1000>; + clocks = <&osc27M>; + #clock-cells = <1>; + }; diff --git a/include/dt-bindings/clock/realtek,rtd1295.h b/include/dt-bindings/clock/realtek,rtd1295.h new file mode 100644 index 000000000000..278148bff2ac --- /dev/null +++ b/include/dt-bindings/clock/realtek,rtd1295.h @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2017 Andreas Färber + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ +#ifndef DT_BINDINGS_CLOCK_RTD1295_H +#define DT_BINDINGS_CLOCK_RTD1295_H + +#define RTD1295_CLK_PLL_SCPU 0 +#define RTD1295_CLK_PLL_BUS 1 +#define RTD1295_CLK_PLL_BUS_DIV2 2 +#define RTD1295_CLK_SYS 3 +#define RTD1295_CLK_PLL_BUS_H 4 +#define RTD1295_CLK_SYSH 5 +#define RTD1295_CLK_PLL_DDSA 6 +#define RTD1295_CLK_PLL_DDSB 7 +#define RTD1295_CLK_PLL_VODMA 8 +#define RTD1295_CLK_PLL_VE1 9 +#define RTD1295_CLK_PLL_VE2 10 +#define RTD1295_CLK_PLL_GPU 14 +#define RTD1295_CLK_PLL_ACPU 15 + +#define RTD1295_CLK_EN_BASE 16 +#define RTD1295_CLK_EN_MISC (RTD1295_CLK_EN_BASE + 0) +#define RTD1295_CLK_EN_PCIE0 (RTD1295_CLK_EN_BASE + 1) +#define RTD1295_CLK_EN_SATA_0 (RTD1295_CLK_EN_BASE + 2) +#define RTD1295_CLK_EN_GSPI (RTD1295_CLK_EN_BASE + 3) +#define RTD1295_CLK_EN_USB (RTD1295_CLK_EN_BASE + 4) +#define RTD1295_CLK_EN_PCR (RTD1295_CLK_EN_BASE + 5) +#define RTD1295_CLK_EN_ISO_MISC (RTD1295_CLK_EN_BASE + 6) +#define RTD1295_CLK_EN_SATA_ALIVE_0 (RTD1295_CLK_EN_BASE + 7) +#define RTD1295_CLK_EN_HDMI (RTD1295_CLK_EN_BASE + 8) +#define RTD1295_CLK_EN_ETN (RTD1295_CLK_EN_BASE + 9) +#define RTD1295_CLK_EN_AIO (RTD1295_CLK_EN_BASE + 10) +#define RTD1295_CLK_EN_GPU (RTD1295_CLK_EN_BASE + 11) +#define RTD1295_CLK_EN_VE1 (RTD1295_CLK_EN_BASE + 12) +#define RTD1295_CLK_EN_VE2 (RTD1295_CLK_EN_BASE + 13) +#define RTD1295_CLK_EN_TVE (RTD1295_CLK_EN_BASE + 14) +#define RTD1295_CLK_EN_VO (RTD1295_CLK_EN_BASE + 15) +#define RTD1295_CLK_EN_LVDS (RTD1295_CLK_EN_BASE + 16) +#define RTD1295_CLK_EN_SE (RTD1295_CLK_EN_BASE + 17) +#define RTD1295_CLK_EN_DCU (RTD1295_CLK_EN_BASE + 18) +#define RTD1295_CLK_EN_CP (RTD1295_CLK_EN_BASE + 19) +#define RTD1295_CLK_EN_MD (RTD1295_CLK_EN_BASE + 20) +#define RTD1295_CLK_EN_TP (RTD1295_CLK_EN_BASE + 21) +#define RTD1295_CLK_EN_RSA (RTD1295_CLK_EN_BASE + 22) +#define RTD1295_CLK_EN_NF (RTD1295_CLK_EN_BASE + 23) +#define RTD1295_CLK_EN_EMMC (RTD1295_CLK_EN_BASE + 24) +#define RTD1295_CLK_EN_CR (RTD1295_CLK_EN_BASE + 25) +#define RTD1295_CLK_EN_SDIO_IP (RTD1295_CLK_EN_BASE + 26) +#define RTD1295_CLK_EN_MIPI (RTD1295_CLK_EN_BASE + 27) +#define RTD1295_CLK_EN_EMMC_IP (RTD1295_CLK_EN_BASE + 28) +#define RTD1295_CLK_EN_VE3 (RTD1295_CLK_EN_BASE + 29) +#define RTD1295_CLK_EN_SDIO (RTD1295_CLK_EN_BASE + 30) +#define RTD1295_CLK_EN_SD_IP (RTD1295_CLK_EN_BASE + 31) + +#define RTD1295_CLK_EN_BASE2 (RTD1295_CLK_EN_BASE + 32) +#define RTD1295_CLK_EN_NAT (RTD1295_CLK_EN_BASE2 + 0) +#define RTD1295_CLK_EN_MISC_I2C_5 (RTD1295_CLK_EN_BASE2 + 1) +#define RTD1295_CLK_EN_SCPU (RTD1295_CLK_EN_BASE2 + 2) +#define RTD1295_CLK_EN_JPEG (RTD1295_CLK_EN_BASE2 + 3) +#define RTD1295_CLK_EN_APU (RTD1295_CLK_EN_BASE2 + 4) +#define RTD1295_CLK_EN_PCIE1 (RTD1295_CLK_EN_BASE2 + 5) +#define RTD1295_CLK_EN_MISC_SC (RTD1295_CLK_EN_BASE2 + 6) +#define RTD1295_CLK_EN_CBUS_TX (RTD1295_CLK_EN_BASE2 + 7) +#define RTD1295_CLK_EN_MISC_RTC (RTD1295_CLK_EN_BASE2 + 10) +#define RTD1295_CLK_EN_MISC_I2C_4 (RTD1295_CLK_EN_BASE2 + 13) +#define RTD1295_CLK_EN_MISC_I2C_3 (RTD1295_CLK_EN_BASE2 + 14) +#define RTD1295_CLK_EN_MISC_I2C_2 (RTD1295_CLK_EN_BASE2 + 15) +#define RTD1295_CLK_EN_MISC_I2C_1 (RTD1295_CLK_EN_BASE2 + 16) +#define RTD1295_CLK_EN_AIO_AU_CODEC (RTD1295_CLK_EN_BASE2 + 17) +#define RTD1295_CLK_EN_AIO_MOD (RTD1295_CLK_EN_BASE2 + 18) +#define RTD1295_CLK_EN_AIO_DA (RTD1295_CLK_EN_BASE2 + 19) +#define RTD1295_CLK_EN_AIO_HDMI (RTD1295_CLK_EN_BASE2 + 20) +#define RTD1295_CLK_EN_AIO_SPDIF (RTD1295_CLK_EN_BASE2 + 21) +#define RTD1295_CLK_EN_AIO_I2S (RTD1295_CLK_EN_BASE2 + 22) +#define RTD1295_CLK_EN_AIO_MCLK (RTD1295_CLK_EN_BASE2 + 23) +#define RTD1295_CLK_EN_HDMIRX (RTD1295_CLK_EN_BASE2 + 24) +#define RTD1295_CLK_EN_SATA_1 (RTD1295_CLK_EN_BASE2 + 25) +#define RTD1295_CLK_EN_SATA_ALIVE_1 (RTD1295_CLK_EN_BASE2 + 26) +#define RTD1295_CLK_EN_UR2 (RTD1295_CLK_EN_BASE2 + 27) +#define RTD1295_CLK_EN_UR1 (RTD1295_CLK_EN_BASE2 + 28) +#define RTD1295_CLK_EN_FAN (RTD1295_CLK_EN_BASE2 + 29) +#define RTD1295_CLK_EN_DCPHY_0 (RTD1295_CLK_EN_BASE2 + 30) +#define RTD1295_CLK_EN_DCPHY_1 (RTD1295_CLK_EN_BASE2 + 31) + +#define RTD1295_ISO_CLK_EN_MISC_CEC0 2 +#define RTD1295_ISO_CLK_EN_CBUSRX_SYS 3 +#define RTD1295_ISO_CLK_EN_CBUSTX_SYS 4 +#define RTD1295_ISO_CLK_EN_CBUS_SYS 5 +#define RTD1295_ISO_CLK_EN_CBUS_OSC 6 +#define RTD1295_ISO_CLK_EN_MISC_IR 7 +#define RTD1295_ISO_CLK_EN_MISC_UR0 8 +#define RTD1295_ISO_CLK_EN_I2C_0 9 +#define RTD1295_ISO_CLK_EN_I2C_1 10 +#define RTD1295_ISO_CLK_EN_ETN_250M 11 +#define RTD1295_ISO_CLK_EN_ETN_SYS 12 + +#endif