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[209.132.180.67]) by mx.google.com with ESMTP id r14si596314pli.737.2017.08.16.06.46.48; Wed, 16 Aug 2017 06:46:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=iYUTMAxC; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752565AbdHPNqq (ORCPT + 26 others); Wed, 16 Aug 2017 09:46:46 -0400 Received: from fllnx209.ext.ti.com ([198.47.19.16]:33020 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752536AbdHPNql (ORCPT ); Wed, 16 Aug 2017 09:46:41 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v7GDjde5016294; Wed, 16 Aug 2017 08:45:39 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1502891139; bh=42fk0QQS6CgtUVkuCl+OUcIH35Tp6zPRx6PF9t71ukY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=iYUTMAxCtkPfGXItOwqUmxZ4qzzfst6iepJbPnjlE5cMJYrrJHDFhh+5AoE/8wY3A xJJBEGBqIMpAMtRraiMr1mCyxv/fTiBlCIobS+xvICAnEj3LH/tIf+GR/uIpugtym7 bj6+U7zr2Zl/Sh0xVhMgqvEA3/LdFpmqu2VpU97E= Received: from DLEE106.ent.ti.com (dlee106.ent.ti.com [157.170.170.36]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7GDjYG7004804; Wed, 16 Aug 2017 08:45:34 -0500 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Wed, 16 Aug 2017 08:45:34 -0500 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Wed, 16 Aug 2017 08:45:33 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Wed, 16 Aug 2017 08:45:33 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7GDjCAZ017583; Wed, 16 Aug 2017 08:45:31 -0500 From: Kishon Vijay Abraham I To: Tony Lindgren CC: , , , , , , Subject: [PATCH v2 07/10] ARM: dts: am572x-idk: Add pinmux configuration for MMC Date: Wed, 16 Aug 2017 19:15:05 +0530 Message-ID: <20170816134508.8887-8-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170816134508.8887-1-kishon@ti.com> References: <20170816134508.8887-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Include dra74x-mmc-iodelay.dtsi which has pinmux and IODelay configuration values for the various MMC modes for dra74x SoC and use it in the pinctrl properties of MMC devicetree nodes present in am572x-idk.dts. Signed-off-by: Kishon Vijay Abraham I --- arch/arm/boot/dts/am572x-idk.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) -- 2.11.0 diff --git a/arch/arm/boot/dts/am572x-idk.dts b/arch/arm/boot/dts/am572x-idk.dts index 5b22944fedad..a578fe97ba3b 100644 --- a/arch/arm/boot/dts/am572x-idk.dts +++ b/arch/arm/boot/dts/am572x-idk.dts @@ -12,6 +12,7 @@ #include #include #include "am57xx-idk-common.dtsi" +#include "dra74x-mmc-iodelay.dtsi" / { model = "TI AM5728 IDK"; @@ -67,6 +68,24 @@ }; }; +&mmc1 { + pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_hs>; + pinctrl-2 = <&mmc1_pins_sdr12>; + pinctrl-3 = <&mmc1_pins_sdr25>; + pinctrl-4 = <&mmc1_pins_sdr50>; + pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>; + pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>; +}; + +&mmc2 { + pinctrl-names = "default", "hs", "ddr_1_8v"; + pinctrl-0 = <&mmc2_pins_default>; + pinctrl-1 = <&mmc2_pins_hs>; + pinctrl-2 = <&mmc2_pins_ddr_rev20>; +}; + &omap_dwc3_2 { extcon = <&extcon_usb2>; };