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[209.132.180.67]) by mx.google.com with ESMTP id d2si611929plh.32.2017.08.16.06.49.12; Wed, 16 Aug 2017 06:49:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=lDqHomiZ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752275AbdHPNqC (ORCPT + 26 others); Wed, 16 Aug 2017 09:46:02 -0400 Received: from lelnx194.ext.ti.com ([198.47.27.80]:43973 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752028AbdHPNp4 (ORCPT ); Wed, 16 Aug 2017 09:45:56 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v7GDjVgq020112; Wed, 16 Aug 2017 08:45:31 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1502891131; bh=z5FgT6hV2ftb9HSxUBUnZOToULOXrcwF+5qzNbfKkaM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=lDqHomiZCshuUSiETRCKV+PR0Nj4TsR20OvbNYlIqkPAl8N9+SaImOORiXuSCCu6S gK8aUEnKqNJnXkb+GE0ndxm4PWZq9SMif+5yR3n5j7oUotCIBBjpvqUUdy89kOH49A olHI6UBfHAk6a0sgMPkm4tOJjmn7TPVXxOcnpdOs= Received: from DLEE103.ent.ti.com (dlee103.ent.ti.com [157.170.170.33]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7GDjVfA028376; Wed, 16 Aug 2017 08:45:31 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Wed, 16 Aug 2017 08:45:31 -0500 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Wed, 16 Aug 2017 08:45:31 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Wed, 16 Aug 2017 08:45:31 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7GDjCAY017583; Wed, 16 Aug 2017 08:45:29 -0500 From: Kishon Vijay Abraham I To: Tony Lindgren CC: , , , , , , Subject: [PATCH v2 06/10] ARM: dts: am571x-idk: Add pinmux configuration for MMC Date: Wed, 16 Aug 2017 19:15:04 +0530 Message-ID: <20170816134508.8887-7-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170816134508.8887-1-kishon@ti.com> References: <20170816134508.8887-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Include dra72x-mmc-iodelay.dtsi which has pinmux and IODelay configuration values for the various MMC modes for dra72 SoC and use it in the pinctrl properties of MMC devicetree nodes present in am571x-idk.dts. Signed-off-by: Kishon Vijay Abraham I --- arch/arm/boot/dts/am571x-idk.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) -- 2.11.0 diff --git a/arch/arm/boot/dts/am571x-idk.dts b/arch/arm/boot/dts/am571x-idk.dts index 78c5c7462fcc..debf9464403e 100644 --- a/arch/arm/boot/dts/am571x-idk.dts +++ b/arch/arm/boot/dts/am571x-idk.dts @@ -11,6 +11,7 @@ #include #include #include "am57xx-idk-common.dtsi" +#include "dra72x-mmc-iodelay.dtsi" / { model = "TI AM5718 IDK"; @@ -98,3 +99,21 @@ &pcie1_ep { gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; }; + +&mmc1 { + pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_hs>; + pinctrl-2 = <&mmc1_pins_sdr12>; + pinctrl-3 = <&mmc1_pins_sdr25>; + pinctrl-4 = <&mmc1_pins_sdr50>; + pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>; + pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>; +}; + +&mmc2 { + pinctrl-names = "default", "hs", "ddr_1_8v"; + pinctrl-0 = <&mmc2_pins_default>; + pinctrl-1 = <&mmc2_pins_hs>; + pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>; +};