From patchwork Wed Aug 16 00:38:46 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 110197 Delivered-To: patch@linaro.org Received: by 10.182.109.195 with SMTP id hu3csp184278obb; Tue, 15 Aug 2017 17:40:14 -0700 (PDT) X-Received: by 10.98.59.82 with SMTP id i79mr30249968pfa.37.1502844014327; Tue, 15 Aug 2017 17:40:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1502844014; cv=none; d=google.com; s=arc-20160816; b=pDSq+jqgLwN6R40qQjHo0cx2TiGAk1CsCHZBMMYYxR5YbXskHg2o3LgdwYCtIhdAvZ AGuuyZ8XhZjWgTIzydzSSCi/rbUkHv6SkcgFRJQkYHymDMrEQmlwEdSQA+0BSqMIOnKj fIHEOWw1nrK/xFALJi1ZgB90oPIlk5i+L3n6QK89x4DDblsPEjCp9gpSTqCJMZJf5zBQ YuWVCNv/prrXk7cxPatH//yPVIp0nkdtpTMPyOSEWEVHQrSgRp4DHosMjWwHpRbjdX+8 96kt+an4YAm5QhlvTJ7uI+lRfJJo7W0c+us7IfJ7GH5pvl9oPt1H+LRfbXzXl2jW7kI5 pukQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=6s/HDEeyzxFXtPFGG8E3/RBcIM9VQYrsI9aSK6qFfwo=; b=w7vn4jDjxgq1Rv8NesPDFmsU69eziYoQndbdlrn4L6Yg8cBT2i1cmaIE1RR1H7VEYu lcHB5tnwHXyDPofJ2qu0RYjcNdIMukpvLijlSstaYsEjp1H32YUwDM5R7g/2sDF1lATJ Ipv7QvAaCQbxc8RK6RwuKlObentQI2KpoXacz96hWG0iKGkD4sOoPa+Om/m7X6qToiDw iPDfm/uWpmETAJtby88pYeKCYgaIUEyLxa3kaKGOw1Wpv71TwF0WaCZ039AMXWZ9cuv7 JlTXGqDUz8fHl+yeo/GIIn6/FO/hhjXVf7Rb/1hLS6CFhUTqUVlC/xxFRfHz2wHK802v rK0g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s85si6173950pfa.472.2017.08.15.17.40.14; Tue, 15 Aug 2017 17:40:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753543AbdHPAkL (ORCPT + 26 others); Tue, 15 Aug 2017 20:40:11 -0400 Received: from mx2.suse.de ([195.135.220.15]:45382 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753409AbdHPAjF (ORCPT ); Tue, 15 Aug 2017 20:39:05 -0400 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay1.suse.de (charybdis-ext.suse.de [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id 9BF20AF38; Wed, 16 Aug 2017 00:39:03 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: Philipp Zabel , linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Roc He , =?utf-8?b?6JKL?= =?utf-8?b?5Li955C0?= , =?utf-8?q?Andreas_F=C3=A4rber?= , Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , devicetree@vger.kernel.org Subject: [PATCH 4/5] arm64: dts: realtek: Add RTD1295 UART resets Date: Wed, 16 Aug 2017 02:38:46 +0200 Message-Id: <20170816003847.6208-5-afaerber@suse.de> X-Mailer: git-send-email 2.12.3 In-Reply-To: <20170816003847.6208-1-afaerber@suse.de> References: <20170816003847.6208-1-afaerber@suse.de> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Associate the UART nodes with the corresponding reset controller bits. Signed-off-by: Andreas Färber --- arch/arm64/boot/dts/realtek/rtd1295.dtsi | 3 +++ 1 file changed, 3 insertions(+) -- 2.12.3 diff --git a/arch/arm64/boot/dts/realtek/rtd1295.dtsi b/arch/arm64/boot/dts/realtek/rtd1295.dtsi index 9f1dcd1fa8b3..e777200d84b9 100644 --- a/arch/arm64/boot/dts/realtek/rtd1295.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd1295.dtsi @@ -123,6 +123,7 @@ reg-shift = <2>; reg-io-width = <4>; clock-frequency = <27000000>; + resets = <&iso_reset 8>; status = "disabled"; }; @@ -132,6 +133,7 @@ reg-shift = <2>; reg-io-width = <4>; clock-frequency = <432000000>; + resets = <&reset2 28>; status = "disabled"; }; @@ -141,6 +143,7 @@ reg-shift = <2>; reg-io-width = <4>; clock-frequency = <432000000>; + resets = <&reset2 27>; status = "disabled"; };