From patchwork Wed Aug 16 00:38:45 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 110195 Delivered-To: patch@linaro.org Received: by 10.182.109.195 with SMTP id hu3csp183572obb; Tue, 15 Aug 2017 17:39:14 -0700 (PDT) X-Received: by 10.99.117.30 with SMTP id q30mr29713750pgc.437.1502843954191; Tue, 15 Aug 2017 17:39:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1502843954; cv=none; d=google.com; s=arc-20160816; b=VZDmJjy97x2iDPq15M8ALYytIYzkd64RrNRpgrznqUO5S0eR1+lbdVLfJrAbZqjolR dou+QXUa63ER06JXNaA7ltCX0h8FgzuIc85uLJ3MAnEln5hDHglXRTxF//Th+zOahdeS 1UlMPxUg0tNjATJ0Q+8UJ7Zc5j3zuENG3S22EOkpRYN28Ggj0IAYb5H7fLX7c68309Dz gZXkhs2KwFS4zokLzWGU4WXG30MdlKYvdd7H0+251roHjLKIzBl/ejF2nbOSE2XkXKKI BbS0+HSixNR/TfsYfS6w8kUI4alZJY4FlLaqyqBtuuS0VyUJHNCr4DSnziFOnToD4b0J 3vGA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=mO3b+LzmQTLj/1mJrlnulc0zfvEPDFVpeT3mAPtf6kY=; b=S++03/DgFTBGtLYekHWWSL1E/AnR6oTGYNM/cdUWm0KVUTEJjRR4mhMZr+YxROOm1J dg2qhEnEC5HAOJoeVpLb+0eEeYuvvNrg2t/iUZWEsc7qBf+Tszd5O93XRxFJxtVRjElV K8a0xV7G/pWisIaQFO+P+W+7GRA87B8yeJBktWdb1H11wN7WW9tHoRzxmkDplmeDcRgn /ZRec5gM+sTLW/07AB9rLpSOy9HNDN6oD8IW3JHQoLX/SoOed11eW+T0sKrFjvWhCl01 tQBzdKJnA6CJQqmzAMD9dUwzd65QtBvXslXVMLCTWHyBkr7BW0P9MfcnV7SxU/Bgkk5G JQzA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 17si6212729pfv.598.2017.08.15.17.39.13; Tue, 15 Aug 2017 17:39:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753487AbdHPAjJ (ORCPT + 26 others); Tue, 15 Aug 2017 20:39:09 -0400 Received: from mx2.suse.de ([195.135.220.15]:45400 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753014AbdHPAjH (ORCPT ); Tue, 15 Aug 2017 20:39:07 -0400 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (charybdis-ext.suse.de [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id EA440AF3A; Wed, 16 Aug 2017 00:39:05 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: Philipp Zabel , linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Roc He , =?utf-8?b?6JKL?= =?utf-8?b?5Li955C0?= , =?utf-8?q?Andreas_F=C3=A4rber?= Subject: [PATCH 3/5] reset: Add Realtek RTD1295 driver Date: Wed, 16 Aug 2017 02:38:45 +0200 Message-Id: <20170816003847.6208-4-afaerber@suse.de> X-Mailer: git-send-email 2.12.3 In-Reply-To: <20170816003847.6208-1-afaerber@suse.de> References: <20170816003847.6208-1-afaerber@suse.de> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a per-register reset controller driver. This deals with the fact that not all registers are adjoined. Signed-off-by: Andreas Färber --- drivers/reset/Kconfig | 6 +++ drivers/reset/Makefile | 1 + drivers/reset/reset-rtd129x.c | 100 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 107 insertions(+) create mode 100644 drivers/reset/reset-rtd129x.c -- 2.12.3 diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 52d5251660b9..dbac75e3f82c 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -68,6 +68,12 @@ config RESET_PISTACHIO help This enables the reset driver for ImgTec Pistachio SoCs. +config RESET_RTD129X + bool "Realtek RTD129x Reset Driver" if COMPILE_TEST + default ARCH_REALTEK if ARM64 + help + This enables the reset controller driver for Realtek RTD1295 SoC. + config RESET_SOCFPGA bool "SoCFPGA Reset Driver" if COMPILE_TEST default ARCH_SOCFPGA diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index b62783f50fe5..bca900260a57 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o obj-$(CONFIG_RESET_MESON) += reset-meson.o obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o +obj-$(CONFIG_RESET_RTD129X) += reset-rtd129x.o obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o obj-$(CONFIG_RESET_STM32) += reset-stm32.o obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o diff --git a/drivers/reset/reset-rtd129x.c b/drivers/reset/reset-rtd129x.c new file mode 100644 index 000000000000..d553900096c6 --- /dev/null +++ b/drivers/reset/reset-rtd129x.c @@ -0,0 +1,100 @@ +/* + * Realtek RTD129x reset controller + * + * Copyright (c) 2017 Andreas Färber + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include +#include + +struct rtd129x_reset_controller { + struct reset_controller_dev rcdev; + void __iomem *base; + spinlock_t lock; +}; + +#define to_rtd129x_rcdev(_rcdev) \ + container_of(_rcdev, struct rtd129x_reset_controller, rcdev) + +static int rtd129x_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct rtd129x_reset_controller *data = to_rtd129x_rcdev(rcdev); + unsigned long flags; + u32 reg; + + spin_lock_irqsave(&data->lock, flags); + + reg = readl(data->base); + writel(reg & ~BIT(id), data->base); + + spin_unlock_irqrestore(&data->lock, flags); + + return 0; +} + +static int rtd129x_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct rtd129x_reset_controller *data = to_rtd129x_rcdev(rcdev); + unsigned long flags; + u32 reg; + + spin_lock_irqsave(&data->lock, flags); + + reg = readl(data->base); + writel(reg | BIT(id), data->base); + + spin_unlock_irqrestore(&data->lock, flags); + + return 0; +} + +static const struct reset_control_ops rtd129x_reset_ops = { + .assert = rtd129x_reset_assert, + .deassert = rtd129x_reset_deassert, +}; + +static const struct of_device_id rtd129x_reset_dt_ids[] = { + { .compatible = "realtek,rtd1295-reset" }, + { } +}; + +static int rtd129x_reset_probe(struct platform_device *pdev) +{ + struct rtd129x_reset_controller *data; + struct resource *res; + + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + data->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(data->base)) + return PTR_ERR(data->base); + + spin_lock_init(&data->lock); + + data->rcdev.owner = THIS_MODULE; + data->rcdev.nr_resets = 32; + data->rcdev.ops = &rtd129x_reset_ops; + data->rcdev.of_node = pdev->dev.of_node; + + return devm_reset_controller_register(&pdev->dev, &data->rcdev); +} + +static struct platform_driver rtd129x_reset_driver = { + .probe = rtd129x_reset_probe, + .driver = { + .name = "rtd129x-reset", + .of_match_table = rtd129x_reset_dt_ids, + }, +}; +builtin_platform_driver(rtd129x_reset_driver);