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[209.132.180.67]) by mx.google.com with ESMTP id r68si3958021pfa.50.2017.08.14.02.52.16; Mon, 14 Aug 2017 02:52:16 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZGnY3j95; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752761AbdHNJwO (ORCPT + 25 others); Mon, 14 Aug 2017 05:52:14 -0400 Received: from mail-pg0-f46.google.com ([74.125.83.46]:36500 "EHLO mail-pg0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751720AbdHNJwL (ORCPT ); Mon, 14 Aug 2017 05:52:11 -0400 Received: by mail-pg0-f46.google.com with SMTP id v77so44022012pgb.3 for ; Mon, 14 Aug 2017 02:52:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=YEcd6O9Sh1eSg86rORXukXFs4VJdNv1Q5+OM1Lbe3Bo=; b=ZGnY3j95sO+/qjQRQaJKvKfTNTmyuQba6oQ525ozfIkt/L5wOromvrF0gy1sWzXKcx xWluD9YAk43eYfueO53VhsQs218vakOnPyFbT+XzZ/FkfLSTt51Gt4hBwFiqgadtIWjb 41d+c1WoXsYWaf43UpstEL7VgPEuDFdCtVFIc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YEcd6O9Sh1eSg86rORXukXFs4VJdNv1Q5+OM1Lbe3Bo=; b=Z1n4zidBW8NGDoRUHVm52T1bl/WqVsdb4E6vSyp6w9BBpJA1qS+o/YJmieeRSljNH4 4o3oID1rJdzsFlc3g4CXUKcXbp643wCasMAFE+3k/jlf7DYCq9U6qXlsLt/zZT3XnYVA x8XIOgXYZfLdxNdTCrK6aLOHhYPCRLJQ0eg33p+95FmfaNIvdL0hyZXHyEhoAfdWuK1h lOG1qH0ooD+9fPZ5zH7HO2ZJADhL3bK2yKEGRyR4YrHpImijjTpg/jvxUGcUhwSEwHzH RFat1/n04CUJRCnj4xkq4VbpLis+k/cBfdI45k3UB6113JBEyGjmHvJ8jAWpY4dWSh4m k63w== X-Gm-Message-State: AHYfb5gu/dBBK2j+p65iw4mcPHLmECICPWI7sNZnRz/mYRucR3tE9aG8 //MDZ9Hmk4sRH+Zj X-Received: by 10.84.133.11 with SMTP id 11mr27779862plf.77.1502704330389; Mon, 14 Aug 2017 02:52:10 -0700 (PDT) Received: from docularxu-ThinkPad-T440p.219.146.1.66 ([45.41.135.45]) by smtp.gmail.com with ESMTPSA id e63sm3468674pfc.24.2017.08.14.02.52.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 14 Aug 2017 02:52:09 -0700 (PDT) From: Guodong Xu To: xuwei5@hisilicon.com, robh+dt@kernel.org, mark.rutland@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, keescook@chromium.org, anton@enomsg.org, ccross@android.com, tony.luck@intel.com Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Leo Yan Subject: [PATCH v3 02/10] arm64: dts: hi3660: add L2 cache topology Date: Mon, 14 Aug 2017 17:50:41 +0800 Message-Id: <20170814095049.27701-3-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170814095049.27701-1-guodong.xu@linaro.org> References: <20170814095049.27701-1-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Leo Yan This patch adds the L2 cache topology on 96boards Hikey960. Signed-off-by: Leo Yan --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) -- 2.10.2 diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 8921310..1cdd03b 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -58,6 +58,7 @@ device_type = "cpu"; reg = <0x0 0x0>; enable-method = "psci"; + next-level-cache = <&A53_L2>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; }; @@ -66,6 +67,7 @@ device_type = "cpu"; reg = <0x0 0x1>; enable-method = "psci"; + next-level-cache = <&A53_L2>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; }; @@ -74,6 +76,7 @@ device_type = "cpu"; reg = <0x0 0x2>; enable-method = "psci"; + next-level-cache = <&A53_L2>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; }; @@ -82,6 +85,7 @@ device_type = "cpu"; reg = <0x0 0x3>; enable-method = "psci"; + next-level-cache = <&A53_L2>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; }; @@ -90,6 +94,7 @@ device_type = "cpu"; reg = <0x0 0x100>; enable-method = "psci"; + next-level-cache = <&A73_L2>; cpu-idle-states = < &CPU_NAP &CPU_SLEEP @@ -102,6 +107,7 @@ device_type = "cpu"; reg = <0x0 0x101>; enable-method = "psci"; + next-level-cache = <&A73_L2>; cpu-idle-states = < &CPU_NAP &CPU_SLEEP @@ -114,6 +120,7 @@ device_type = "cpu"; reg = <0x0 0x102>; enable-method = "psci"; + next-level-cache = <&A73_L2>; cpu-idle-states = < &CPU_NAP &CPU_SLEEP @@ -126,6 +133,7 @@ device_type = "cpu"; reg = <0x0 0x103>; enable-method = "psci"; + next-level-cache = <&A73_L2>; cpu-idle-states = < &CPU_NAP &CPU_SLEEP @@ -171,6 +179,14 @@ min-residency-us = <20000>; }; }; + + A53_L2: l2-cache0 { + compatible = "cache"; + }; + + A73_L2: l2-cache1 { + compatible = "cache"; + }; }; gic: interrupt-controller@e82b0000 {