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[68.111.217.79]) by smtp.gmail.com with ESMTPSA id o15sm9928723pgf.22.2017.08.09.13.10.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 09 Aug 2017 13:10:40 -0700 (PDT) From: Bjorn Andersson To: Andy Gross , David Brown Cc: Rob Herring , Mark Rutland , Stephen Boyd , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org Subject: [PATCH v3 3/3] arm64: dts: qcom: Specify dload address for msm8916 and msm8996 Date: Wed, 9 Aug 2017 13:10:33 -0700 Message-Id: <20170809201033.4967-4-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20170809201033.4967-1-bjorn.andersson@linaro.org> References: <20170809201033.4967-1-bjorn.andersson@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On msm8916 and msm8996 boards a secure io-write is used to write the magic for selecting "download mode", specify this address in the DeviceTree. Note that qcom_scm.download_mode=1 must be specified on the kernel command line for the kernel to attempt selecting download mode. Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 ++ arch/arm64/boot/dts/qcom/msm8996.dtsi | 7 +++++++ 2 files changed, 9 insertions(+) -- 2.12.0 diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 039991f80831..b7197f2e7209 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -241,6 +241,8 @@ clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>; clock-names = "core", "bus", "iface"; #reset-cells = <1>; + + qcom,dload-mode = <&tcsr>; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 8f085716e258..2eee6a33f22b 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -261,6 +261,8 @@ firmware { scm { compatible = "qcom,scm-msm8996"; + + qcom,dload-mode = <&tcsr>; }; }; @@ -287,6 +289,11 @@ reg = <0x740000 0x20000>; }; + tcsr: syscon@1937000 { + compatible = "qcom,tcsr-msm8996", "syscon"; + reg = <0x7a0000 0x18000>; + }; + intc: interrupt-controller@9bc0000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>;