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[209.132.180.67]) by mx.google.com with ESMTP id q205si4772637pfq.133.2017.08.07.07.52.11; Mon, 07 Aug 2017 07:52:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=MUi+b2n1; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751920AbdHGOwJ (ORCPT + 25 others); Mon, 7 Aug 2017 10:52:09 -0400 Received: from mail-pg0-f44.google.com ([74.125.83.44]:35815 "EHLO mail-pg0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751364AbdHGOwH (ORCPT ); Mon, 7 Aug 2017 10:52:07 -0400 Received: by mail-pg0-f44.google.com with SMTP id v189so2578671pgd.2 for ; Mon, 07 Aug 2017 07:52:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=ec0e2Nq7ie2h6qzkkcAuRYquTK7yvRG0FnBEZ5KqHZM=; b=MUi+b2n1nfeAGzhAZEPiyazF+Nl2dIUEcBH/j5aJ/qGMn/7ox9zfUtPMG5dl83jaM5 DmzuubGM4BInnIPFZjkBFFZINMqJE+1o/YGJjYQvkSwlEWOEeoksaCMMU0a1e6RhDvdF 9MR9SHqxdAd6Ygg0dZ0xxIveOJZq5vrnSPVhw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=ec0e2Nq7ie2h6qzkkcAuRYquTK7yvRG0FnBEZ5KqHZM=; b=SUcVTFSC8ViMbP9A7f7keFBguJJ8tIqIIRhXX1XoTa7dwKhX/0wTDc/O0GvpwhdBtS B5X29oqWsh95QoLUYAqxUFPbeM4Mmw40SKFTNXYLcTy10DdQ3YkXV04H106lLmoG8EtN 5TFZyuwRd/ZyYUcrbL7XKYkCJeqLj+MMdUzW2sS0hzERjLu+ImhbFLWP1lpgyyBGFEds Mit5F8OudMfKER9+K0kwOcJmiOPTwJ0H8o8tbLWcvGbG9K2sajx7442SUQ+vvSwp4KDq aqyh8/xvXLmqS2bA4s7QPRf1gKCTNhdQO3G7HqG9jyu6TaIYKQ6nSxhi0DkaVkmETkrT QHVg== X-Gm-Message-State: AHYfb5h7NBTZ1gZN+U+8S380jluUO7/vxEjQ0kqiWS8MTCNU4J0JirjB oxtHZTKpua7kFbsQ X-Received: by 10.98.16.68 with SMTP id y65mr845361pfi.165.1502117526764; Mon, 07 Aug 2017 07:52:06 -0700 (PDT) Received: from docularxu-ThinkPad-T440p.219.146.1.66 ([45.56.159.229]) by smtp.gmail.com with ESMTPSA id p80sm16871832pfa.19.2017.08.07.07.52.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Aug 2017 07:52:06 -0700 (PDT) From: Guodong Xu To: mturquette@baylibre.com, sboyd@codeaurora.org Cc: chenjun14@huawei.com, zhongkaihua@huawei.com, zhangfei.gao@linaro.org, leo.yan@linaro.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Guodong Xu Subject: [PATCH] clk: hi3660: fix incorrect uart3 clock freqency Date: Mon, 7 Aug 2017 22:51:56 +0800 Message-Id: <20170807145156.7880-1-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Zhong Kaihua UART3 clock rate is doubled in previous commit. This error is not detected until recently a mezzanine board which makes real use of uart3 port (through LS connector of 96boards) was setup and tested on hi3660-hikey960 board. This patch changes clock source rate of clk_factor_uart3 to 100000000. Signed-off-by: Zhong Kaihua Signed-off-by: Guodong Xu --- drivers/clk/hisilicon/clk-hi3660.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.10.2 diff --git a/drivers/clk/hisilicon/clk-hi3660.c b/drivers/clk/hisilicon/clk-hi3660.c index a18258e..f404199 100644 --- a/drivers/clk/hisilicon/clk-hi3660.c +++ b/drivers/clk/hisilicon/clk-hi3660.c @@ -34,7 +34,7 @@ static const struct hisi_fixed_rate_clock hi3660_fixed_rate_clks[] = { /* crgctrl */ static const struct hisi_fixed_factor_clock hi3660_crg_fixed_factor_clks[] = { - { HI3660_FACTOR_UART3, "clk_factor_uart3", "iomcu_peri0", 1, 8, 0, }, + { HI3660_FACTOR_UART3, "clk_factor_uart3", "iomcu_peri0", 1, 16, 0, }, { HI3660_CLK_FACTOR_MMC, "clk_factor_mmc", "clkin_sys", 1, 6, 0, }, { HI3660_CLK_GATE_I2C0, "clk_gate_i2c0", "clk_i2c0_iomcu", 1, 4, 0, }, { HI3660_CLK_GATE_I2C1, "clk_gate_i2c1", "clk_i2c1_iomcu", 1, 4, 0, },