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[209.132.180.67]) by mx.google.com with ESMTP id p27si2498757pli.332.2017.08.01.08.49.24; Tue, 01 Aug 2017 08:49:25 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.b=IiZXzWs9; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751833AbdHAPtV (ORCPT + 26 others); Tue, 1 Aug 2017 11:49:21 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:32033 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751375AbdHAPtR (ORCPT ); Tue, 1 Aug 2017 11:49:17 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v71FmnWV019439; Tue, 1 Aug 2017 10:48:49 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1501602529; bh=r5Vgg94VX/fElj/eouRZ5FEaVB2nwsGRm56kbSEiRiE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=IiZXzWs9MtgIoaZ0o1wO4gww58TCiyzZseGp8UXnjmHypmq0LhgGcheWxxabedrqS qojkku11VVF6577qaNJfEORKy78a3N4SraAkDkON6qqa1Vj4VG/kunlTUhrk7fhOJA +/jgzqWpsbZkLy2jEqn5yS+4ZjbjzQI3arknlsAM= Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v71FmneW001104; Tue, 1 Aug 2017 10:48:49 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.294.0; Tue, 1 Aug 2017 10:48:48 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v71FmmjZ020938; Tue, 1 Aug 2017 10:48:48 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.153]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id v71Fmm323826; Tue, 1 Aug 2017 10:48:48 -0500 (CDT) From: Suman Anna To: Bjorn Andersson , Ohad Ben-Cohen , Rob Herring CC: Mark Rutland , , , Sekhar Nori , Robert Tivy , , , Suman Anna Subject: [PATCH v2 3/4] dt-bindings: remoteproc: Add bindings for Davinci DSP processors Date: Tue, 1 Aug 2017 10:48:43 -0500 Message-ID: <20170801154844.24662-4-s-anna@ti.com> X-Mailer: git-send-email 2.13.1 In-Reply-To: <20170801154844.24662-1-s-anna@ti.com> References: <20170801154844.24662-1-s-anna@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the device tree bindings document for the DSP processor subsystem devices on TI Davinci DA8xx/OMAP-L13x SoCs. Signed-off-by: Suman Anna --- v2: - Updated the patch header - Revised the binding status statement slightly - Updated the example to address Rob's comments - No changes in properties description themselves v1: https://patchwork.kernel.org/patch/9751269/ .../bindings/remoteproc/ti,davinci-rproc.txt | 86 ++++++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 Documentation/devicetree/bindings/remoteproc/ti,davinci-rproc.txt -- 2.13.1 diff --git a/Documentation/devicetree/bindings/remoteproc/ti,davinci-rproc.txt b/Documentation/devicetree/bindings/remoteproc/ti,davinci-rproc.txt new file mode 100644 index 000000000000..e44a97e21164 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/ti,davinci-rproc.txt @@ -0,0 +1,86 @@ +TI Davinci DSP devices +======================= + +Binding status: Unstable - Subject to changes for DT representation of clocks + and resets + +The TI Davinci family of SoCs usually contains a TI DSP Core sub-system that +is used to offload some of the processor-intensive tasks or algorithms, for +achieving various system level goals. + +The processor cores in the sub-system usually contain additional sub-modules +like L1 and/or L2 caches/SRAMs, an Interrupt Controller, an external memory +controller, a dedicated local power/sleep controller etc. The DSP processor +core used in Davinci SoCs is usually a C674x DSP CPU. + +DSP Device Node: +================ +Each DSP Core sub-system is represented as a single DT node. + +Required properties: +-------------------- +The following are the mandatory properties: + +- compatible: Should be one of the following, + "ti,da850-dsp" for DSPs on OMAP-L138 SoCs + +- reg: Should contain an entry for each value in 'reg-names'. + Each entry should have the memory region's start address + and the size of the region, the representation matching + the parent node's '#address-cells' and '#size-cells' values. + +- reg-names: Should contain strings with the following names, each + representing a specific internal memory region or a + specific register space, + "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig_base" + +- interrupts: Should contain the interrupt number used to receive the + interrupts from the DSP. The value should follow the + interrupt-specifier format as dictated by the + 'interrupt-parent' node. + +- memory-region: phandle to the reserved memory node to be associated + with the remoteproc device. The reserved memory node + can be a CMA memory node, and should be defined as + per the bindings in + Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt + +Optional properties: +-------------------- +- interrupt-parent: phandle to the interrupt controller node. This property + is needed if the device node hierarchy doesn't have an + interrupt controller. + + +Example: +-------- + + /* DSP Reserved Memory node */ + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dsp_memory_region: dsp-memory@c3000000 { + compatible = "shared-dma-pool"; + reg = <0xc3000000 0x1000000>; + reusable; + }; + }; + + /* DSP node */ + { + dsp: dsp@11800000 { + compatible = "ti,da850-dsp"; + reg = <0x11800000 0x40000>, + <0x11e00000 0x8000>, + <0x11f00000 0x8000>, + <0x01c14044 0x4>, + <0x01c14174 0x8>; + reg-names = "l2sram", "l1pram", "l1dram", "host1cfg", + "chipsig"; + interrupt-parent = <&intc>; + interrupts = <28>; + memory-region = <&dsp_memory_region>; + }; + };