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[209.132.180.67]) by mx.google.com with ESMTP id m4si78077pgn.260.2017.06.15.06.07.45; Thu, 15 Jun 2017 06:07:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=redhat.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752204AbdFONHi (ORCPT + 25 others); Thu, 15 Jun 2017 09:07:38 -0400 Received: from mx1.redhat.com ([209.132.183.28]:60840 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750923AbdFONHg (ORCPT ); Thu, 15 Jun 2017 09:07:36 -0400 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 965EDC0587D8; Thu, 15 Jun 2017 13:07:35 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 965EDC0587D8 Authentication-Results: ext-mx08.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx08.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=hdegoede@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com 965EDC0587D8 Received: from shalem.localdomain.com (ovpn-117-239.ams2.redhat.com [10.36.117.239]) by smtp.corp.redhat.com (Postfix) with ESMTP id 7950982AED; Thu, 15 Jun 2017 13:07:34 +0000 (UTC) From: Hans de Goede To: Lee Jones Cc: Hans de Goede , linux-kernel@vger.kernel.org, Arnd Bergmann Subject: [PATCH v2 1/2] mfd: intel_soc_pmic: use 'depends on' instead of 'select' Date: Thu, 15 Jun 2017 15:07:31 +0200 Message-Id: <20170615130732.6769-1-hdegoede@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.32]); Thu, 15 Jun 2017 13:07:35 +0000 (UTC) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Arnd Bergmann I ran into a build error on ARM with a platform that has a non-standard clk implementation: drivers/clk/clk.o: In function `clk_disable': clk.c:(.text.clk_disable+0x0): multiple definition of `clk_disable' arch/arm/mach-omap1/clock.o:clock.c:(.text.clk_disable+0x0): first defined here drivers/clk/clk.o: In function `clk_enable': clk.c:(.text.clk_enable+0x0): multiple definition of `clk_enable' arch/arm/mach-omap1/clock.o:clock.c:(.text.clk_enable+0x0): first defined here The problem is a device driver that uses 'select COMMON_CLK', which is generally a bad idea: selecting a subsystem should only be done from a platform, otherwise we run into circular dependencies. The same driver also selects 'GPIOLIB' and 'I2C', which has a similar effect. This turns all three into 'depends on', as it should be. Finally, we can limit the build to x86, unless we are compile testing. Fixes: 5f125f1f5705 ("mfd: intel_soc_pmic: Select designware i2c-bus driver") Signed-off-by: Arnd Bergmann Signed-off-by: Hans de Goede --- Changes in v2: -Split into 2 seperate patches for config INTEL_SOC_PMIC and config INTEL_SOC_PMIC_CHTWC --- drivers/mfd/Kconfig | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) -- 2.13.0 diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 95e868360e9a..2499f8b5135a 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -453,14 +453,12 @@ config LPC_SCH config INTEL_SOC_PMIC bool "Support for Crystal Cove PMIC" - depends on HAS_IOMEM - select GPIOLIB - select I2C + depends on HAS_IOMEM && I2C=y && GPIOLIB && COMMON_CLK + depends on X86 || COMPILE_TEST select MFD_CORE select REGMAP_I2C select REGMAP_IRQ - select COMMON_CLK - select I2C_DESIGNWARE_PLATFORM + select I2C_DESIGNWARE_PLATFORM if ACPI help Select this option to enable support for Crystal Cove PMIC on some Intel SoC systems. The PMIC provides ADC, GPIO,