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[209.132.180.67]) by mx.google.com with ESMTP id n34si1305188pld.268.2017.06.14.20.07.00; Wed, 14 Jun 2017 20:07:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=aMvJTNpZ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752700AbdFODGr (ORCPT + 25 others); Wed, 14 Jun 2017 23:06:47 -0400 Received: from mail-pf0-f175.google.com ([209.85.192.175]:35050 "EHLO mail-pf0-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752140AbdFODGp (ORCPT ); Wed, 14 Jun 2017 23:06:45 -0400 Received: by mail-pf0-f175.google.com with SMTP id l89so1392215pfi.2 for ; Wed, 14 Jun 2017 20:06:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=W4L2d8u22c6yygXQJRk+Sqhtqu9yLqxVCuULdrLlfyQ=; b=aMvJTNpZACKHuAcMIi7cS2M+CwqKdBZgEVeO/4iRM0V5JNJcpi4CkdUKlUIO6hBYrw 1FRX5X2AkMlolWYfVpmwVbPI1VGlsT44NJWyduEGW3NlezUfR23CrcF5Y2CPjjWwqWUk 7C/Qo6O6NeNLI90MmY1rbRDixcEplMXpVQVPg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=W4L2d8u22c6yygXQJRk+Sqhtqu9yLqxVCuULdrLlfyQ=; b=FbW2RD2O6GWRXajXmkuV4VS7SEx9Q5PuMUoPLX/mk9+hyV4KMiOnJtj2umRf0X0/uW R6YHsKnanfKFXgxpDC2bbtTgsevuFVuRlK2Ja0lDQOyelKuu4aO9S94YvC8K9XJStPay GRC+lR2A+Q1R7FqhzTDjBzxPf53No4UUxRGYwddStlMabefHlLKvTSK2EUjSfOGoa5jp 2zij78ry3RKe+j9A8/nI7vHGQqP6SHn8VrsT8uloa46R4wYVp214BWSVn7sS8xZIKEnh bTvX0SvhwWIydxdP2u2ykB1vTQJWYVSyg/mebb8s0C72iI2bEih93DTo/ytRfsIfVME7 GAzw== X-Gm-Message-State: AKS2vOy1yFP9p4ShP4EUYzjteS/zKz9sSChCk6PazCNVv8V2UiBR0WMv N9PYjeR8AVVnROqW X-Received: by 10.84.137.165 with SMTP id 34mr3564647pln.167.1497495999816; Wed, 14 Jun 2017 20:06:39 -0700 (PDT) Received: from localhost.localdomain ([45.56.159.17]) by smtp.gmail.com with ESMTPSA id y65sm2156656pgd.33.2017.06.14.20.06.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Jun 2017 20:06:39 -0700 (PDT) From: Guodong Xu To: lee.jones@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, lgirdwood@gmail.com, broonie@kernel.org, khilman@baylibre.com, arnd@arndb.de, gregory.clement@free-electrons.com, horms+renesas@verge.net.au, olof@lixom.net, thomas.petazzoni@free-electrons.com, yamada.masahiro@socionext.com, riku.voipio@linaro.org, treding@nvidia.com, krzk@kernel.org, eric@anholt.net, damm+renesas@opensource.se, ard.biesheuvel@linaro.org, linus.walleij@linaro.org, geert+renesas@glider.be Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, hw.wangxiaoyin@hisilicon.com, Guodong Xu Subject: [PATCH v4 12/20] arm64: dts: hi3660: add spi device nodes Date: Thu, 15 Jun 2017 11:04:09 +0800 Message-Id: <20170615030417.14059-13-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170615030417.14059-1-guodong.xu@linaro.org> References: <20170615030417.14059-1-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Wang Xiaoyin Add spi2 and spi3 device nodes for hi3660, and enable them for hikey960. On HiKey960: - SPI2 is wired out through low speed expansion connector. - SPI3 is wired out through high speed expansion connector. Signed-off-by: Wang Xiaoyin Signed-off-by: Guodong Xu --- arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 12 +++++++++ arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 30 +++++++++++++++++++++++ 2 files changed, 42 insertions(+) -- 2.10.2 diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts index 9ecf6c6..ca448f0 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts @@ -142,3 +142,15 @@ label = "LS-UART1"; status = "okay"; }; + +&spi2 { + /* On Low speed expansion */ + label = "LS-SPI0"; + status = "okay"; +}; + +&spi3 { + /* On High speed expansion */ + label = "HS-SPI1"; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 3b2a3a7..a6b91f1 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -713,5 +713,35 @@ clocks = <&sctrl HI3660_PCLK_AO_GPIO6>; clock-names = "apb_pclk"; }; + + spi2: spi@ffd68000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0xffd68000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>; + clock-names = "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pmx_func>; + num-cs = <1>; + cs-gpios = <&gpio27 2 0>; + status = "disabled"; + }; + + spi3: spi@ff3b3000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0xff3b3000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>; + clock-names = "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi3_pmx_func>; + num-cs = <1>; + cs-gpios = <&gpio18 5 0>; + status = "disabled"; + }; }; };