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[209.132.180.67]) by mx.google.com with ESMTP id 33si168406plk.159.2017.06.14.01.25.35; Wed, 14 Jun 2017 01:25:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=fuETlLuM; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754727AbdFNIZa (ORCPT + 25 others); Wed, 14 Jun 2017 04:25:30 -0400 Received: from mail-pg0-f51.google.com ([74.125.83.51]:33104 "EHLO mail-pg0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932095AbdFNIZ0 (ORCPT ); Wed, 14 Jun 2017 04:25:26 -0400 Received: by mail-pg0-f51.google.com with SMTP id f185so72602336pgc.0 for ; Wed, 14 Jun 2017 01:25:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=l8HEG60ACS51qmx+5dpnRvo8Cd2RySFdr2XUItZtdDs=; b=fuETlLuMkRqb+WvKK38oCTdw21HcTloU22Nyp2SEsd9NjVxkeljQtYZyqIgr9Y2qAW LJmYIARp4trqqPyCl5O6aWtCRrIGUcPWmJeIkRL8+WlJ+m8JoQF1nyenQu/E0ofN4u61 S34tro9r5aOidmReod8EbjqkFyiu/wsi39OTs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=l8HEG60ACS51qmx+5dpnRvo8Cd2RySFdr2XUItZtdDs=; b=ZkpWrRO0XwhRK0Oyf1gYlO8MycHlIrM9EX3MUDnRMXBpCOHNIcbTN8jGPOZzMd89yN gtRlm99HJ1FqlXhuM2i2KUZ9oSr8Mmm9b3OuxV5WtwPpkcluoKpC2O5s0oorgNNTMBFl qopOMTeZIzyLUp83dy16hKp9M5gLVwXjMpdMLlhL9qXNAU0GUtG9PaZndY/CQ+FA3Tu+ 6dC4NOUci6cw6KwcJrla5M7l3AWEoRMvGqBQInckvtlwZU7eSGiOExgivRUIYkl/kS4X JyJDa59ebtglWoBcxTISZ5wkjq/rvSB2C57MxQatWbeyn6VICFesc9R20H+Z3EPEFDms GUoQ== X-Gm-Message-State: AKS2vOxkHBwS+HBT/ecHl/qsc9zmICoOTL8BAX7abmrEAmVMuZsaryW1 9vmVfPbB9PfapVkw X-Received: by 10.98.39.2 with SMTP id n2mr3036103pfn.182.1497428726071; Wed, 14 Jun 2017 01:25:26 -0700 (PDT) Received: from docularxu-ThinkPad-T440p.219.146.1.66 ([45.56.159.99]) by smtp.gmail.com with ESMTPSA id h14sm766802pfh.71.2017.06.14.01.25.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Jun 2017 01:25:25 -0700 (PDT) From: Guodong Xu To: robh+dt@kernel.org, mark.rutland@arm.com, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, wangkefeng.wang@huawei.com, xuejiancheng@hisilicon.com, peter.griffin@linaro.org, puck.chen@hisilicon.com, lee.jones@linaro.org, ulf.hansson@linaro.org, bhelgaas@google.com, arnd@arndb.de Cc: zhangfei.gao@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org, linux-pci@vger.kernel.org, Xiaowei Song Subject: [PATCH v3 15/21] dt-bindings: PCI: hisi: Add document for PCIe of Kirin SoCs Date: Wed, 14 Jun 2017 16:23:32 +0800 Message-Id: <20170614082338.15673-16-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170614082338.15673-1-guodong.xu@linaro.org> References: <20170614082338.15673-1-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiaowei Song This patch adds document for PCIe of Kirin SoC series. Signed-off-by: Xiaowei Song Acked-by: Rob Herring --- .../devicetree/bindings/pci/kirin-pcie.txt | 50 ++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txt -- 2.10.2 diff --git a/Documentation/devicetree/bindings/pci/kirin-pcie.txt b/Documentation/devicetree/bindings/pci/kirin-pcie.txt new file mode 100644 index 0000000..68ffa0f --- /dev/null +++ b/Documentation/devicetree/bindings/pci/kirin-pcie.txt @@ -0,0 +1,50 @@ +HiSilicon Kirin SoCs PCIe host DT description + +Kirin PCIe host controller is based on Designware PCI core. +It shares common functions with PCIe Designware core driver +and inherits common properties defined in +Documentation/devicetree/bindings/pci/designware-pci.txt. + +Additional properties are described here: + +Required properties +- compatible: + "hisilicon,kirin960-pcie" for PCIe of Kirin960 SoC +- reg: Should contain rc_dbi, apb, phy, config registers location and length. +- reg-names: Must include the following entries: + "dbi": controller configuration registers; + "apb": apb Ctrl register defined by Kirin; + "phy": apb PHY register defined by Kirin; + "config": PCIe configuration space registers. +- reset-gpios: The gpio to generate PCIe perst assert and deassert signal. + +Optional properties: + +Example based on kirin960: + + pcie@f4000000 { + compatible = "hisilicon,kirin-pcie"; + reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>, + <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF4000000 0 0x2000>; + reg-names = "dbi","apb","phy", "config"; + bus-range = <0x0 0x1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x02000000 0x0 0x00000000 0x0 0xf5000000 0x0 0x2000000>; + num-lanes = <1>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = <0x0 0 0 1 &gic 0 0 0 282 4>, + <0x0 0 0 2 &gic 0 0 0 283 4>, + <0x0 0 0 3 &gic 0 0 0 284 4>, + <0x0 0 0 4 &gic 0 0 0 285 4>; + clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, + <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, + <&crg_ctrl HI3660_ACLK_GATE_PCIE>; + clock-names = "pcie_phy_ref", "pcie_aux", + "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk"; + reset-gpios = <&gpio11 1 0 >; + };