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[209.132.180.67]) by mx.google.com with ESMTP id f8si30219256pln.39.2017.05.26.00.39.00; Fri, 26 May 2017 00:39:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1035380AbdEZHin (ORCPT + 25 others); Fri, 26 May 2017 03:38:43 -0400 Received: from mail-pf0-f182.google.com ([209.85.192.182]:33346 "EHLO mail-pf0-f182.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1035346AbdEZHif (ORCPT ); Fri, 26 May 2017 03:38:35 -0400 Received: by mail-pf0-f182.google.com with SMTP id e193so4189336pfh.0 for ; Fri, 26 May 2017 00:38:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=eF1NCHRdgYeSwUw/BUsdYReuItV1TCgRBZS89MNcBOk=; b=gu9iI7YU5CrMF4dgiWeaDtHgsXgzr070I6r24/w/hqLQagZom0UMvmSTMUL7ZFHX7U 00ypER0KYZIdYareGF5qyf7KL2B3JqOZxY2M22jtUe3lIyvHKLk/D3GMVnYwXswctOLs 81aIlk3qqOKltBc3pZuHQgyxXBOlj1FpphPJQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=eF1NCHRdgYeSwUw/BUsdYReuItV1TCgRBZS89MNcBOk=; b=GhePxemG4/SQk49C9CvJcGfu8knOjo4SMqIoZTde3VpzNJ35Pxs7Ye1CmYgcgoUwIC LJU854d5TP+NJfPf6/xhe/8lYWQOOqDXuhAMHE9E99PQpAcQS4rjNz0HNpgf5N4oQLRa hl9OnP7rPTLG0dRsLzmhcznbEodC0mT0ve/g+iKZ4vijHlL2Glk71Po4krOx9g8xCiXt UvJ2SFtN9FlrJg5m3tBbDNvgyd6Lb/Pb4ye3b8EjCR//FkfqCF8G4pCgVVDHBDB9vm+E lErINcTPNaKyHGJp990ZRuK5x/h/2Tms1PvaffdGiTWmRkr4q19XkL/BDbjdxvYpkFcS pepg== X-Gm-Message-State: AODbwcDkqEog4JbsFlkk8qKMeBKbcUO6TNk2zVTSqtKBdghb1C3GOyqf kuW0GYHoelLJtFUn X-Received: by 10.98.0.8 with SMTP id 8mr709135pfa.127.1495784314904; Fri, 26 May 2017 00:38:34 -0700 (PDT) Received: from docularxu-ThinkPad-T440p.219.146.1.66 ([45.56.159.222]) by smtp.gmail.com with ESMTPSA id t3sm19106334pfl.60.2017.05.26.00.38.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 26 May 2017 00:38:34 -0700 (PDT) From: Guodong Xu To: mturquette@baylibre.com, sboyd@codeaurora.org, robh+dt@kernel.org, mark.rutland@arm.com Cc: chenjun14@huawei.com, zhongkaihua@huawei.com, zhangfei.gao@linaro.org, leo.yan@linaro.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, John Stultz , Guodong Xu Subject: [PATCH v2 1/3] clk: hi3660: fix wrong parent name of clk_mux_sysbus Date: Fri, 26 May 2017 15:38:19 +0800 Message-Id: <20170526073821.25971-2-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170526073821.25971-1-guodong.xu@linaro.org> References: <20170526073821.25971-1-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Chen Jun Parent name of clk_mux_sysbus is not correct. This patch fixes it. Signed-off-by: Chen Jun Signed-off-by: John Stultz Signed-off-by: Guodong Xu --- drivers/clk/hisilicon/clk-hi3660.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) -- 2.10.2 diff --git a/drivers/clk/hisilicon/clk-hi3660.c b/drivers/clk/hisilicon/clk-hi3660.c index 96a9697..143ce0c 100644 --- a/drivers/clk/hisilicon/clk-hi3660.c +++ b/drivers/clk/hisilicon/clk-hi3660.c @@ -206,6 +206,8 @@ static const struct hisi_gate_clock hi3660_crgctrl_gate_clks[] = { }; static const char *const +clk_mux_sysbus_p[] = {"clk_ppll1", "clk_ppll0"}; +static const char *const clk_mux_sdio_sys_p[] = {"clk_factor_mmc", "clk_div_sdio",}; static const char *const clk_mux_sd_sys_p[] = {"clk_factor_mmc", "clk_div_sd",}; @@ -239,8 +241,8 @@ static const char *const clk_mux_i2c_p[] = {"clkin_sys", "clk_div_i2c",}; static const struct hisi_mux_clock hi3660_crgctrl_mux_clks[] = { - { HI3660_CLK_MUX_SYSBUS, "clk_mux_sysbus", clk_mux_sdio_sys_p, - ARRAY_SIZE(clk_mux_sdio_sys_p), CLK_SET_RATE_PARENT, 0xac, 0, 1, + { HI3660_CLK_MUX_SYSBUS, "clk_mux_sysbus", clk_mux_sysbus_p, + ARRAY_SIZE(clk_mux_sysbus_p), CLK_SET_RATE_PARENT, 0xac, 0, 1, CLK_MUX_HIWORD_MASK, }, { HI3660_CLK_MUX_UART0, "clk_mux_uart0", clk_mux_uart0_p, ARRAY_SIZE(clk_mux_uart0_p), CLK_SET_RATE_PARENT, 0xac, 2, 1,