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[209.132.180.67]) by mx.google.com with ESMTP id a186si7621246pge.285.2017.05.19.01.28.29; Fri, 19 May 2017 01:28:30 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755608AbdESI2W (ORCPT + 25 others); Fri, 19 May 2017 04:28:22 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:10384 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751772AbdESISL (ORCPT ); Fri, 19 May 2017 04:18:11 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v4J8HdxF018259; Fri, 19 May 2017 03:17:39 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1495181859; bh=1j8TDwUEHSPp/y0FvT8FpXznA+XPyn6smnOg/f8kWRQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=vuTsfZMeTBCu2sg40jcvrSNQohXNnc7MxLFhVhwq1BuP061VoXxlRWR7wGtFoP1bO EzDRpSGywZob+wHleCmzC+qqGxl3laMhccTjlt9YlbWf7Dr3BywYsfQMEsLs4DbSth GqjVErR2fIhLzMh4aVCBEZnG/uJFtVotazRCXgFM= Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v4J8Hdfp028718; Fri, 19 May 2017 03:17:39 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.294.0; Fri, 19 May 2017 03:17:38 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v4J8FfQW009185; Fri, 19 May 2017 03:17:34 -0500 From: Kishon Vijay Abraham I To: Ulf Hansson , Rob Herring , Tony Lindgren CC: , , , , , , Jonathan Corbet , Mark Rutland , Russell King , , Subject: [PATCH 25/41] ARM: dts: dra7-evm: Add pinmux configuration for MMC Date: Fri, 19 May 2017 13:45:25 +0530 Message-ID: <20170519081541.26753-26-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170519081541.26753-1-kishon@ti.com> References: <20170519081541.26753-1-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Include dra74x-mmc-iodelay.dtsi which has pinmux and IODelay configuration values for the various MMC modes for dra74 SoC and use it in the pinctrl properties of MMC devicetree nodes present in dra7-evm. Signed-off-by: Kishon Vijay Abraham I --- arch/arm/boot/dts/dra7-evm.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) -- 2.11.0 diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index fbcb3199defd..64955e8f06d2 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -8,6 +8,7 @@ /dts-v1/; #include "dra74x.dtsi" +#include "dra74x-mmc-iodelay.dtsi" #include #include #include @@ -451,6 +452,16 @@ * is always hardwired. */ cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50-rev11", "sdr104-rev11", "ddr50", "sdr104"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_hs>; + pinctrl-2 = <&mmc1_pins_sdr12>; + pinctrl-3 = <&mmc1_pins_sdr25>; + pinctrl-4 = <&mmc1_pins_sdr50>; + pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev11_conf>; + pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev11_conf>; + pinctrl-7 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>; + pinctrl-8 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>; }; &mmc2 { @@ -459,6 +470,13 @@ pinctrl-0 = <&mmc2_pins_default>; vmmc-supply = <&evm_1v8_sw>; bus-width = <8>; + pinctrl-names = "default", "hs", "ddr_1_8v-rev11", "ddr_1_8v", "hs200_1_8v-rev11", "hs200_1_8v"; + pinctrl-0 = <&mmc2_pins_default>; + pinctrl-1 = <&mmc2_pins_hs>; + pinctrl-2 = <&mmc2_pins_ddr_1_8v_rev11 &mmc2_iodelay_ddr_1_8v_rev11_conf>; + pinctrl-3 = <&mmc2_pins_ddr_rev20>; + pinctrl-4 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev11_conf>; + pinctrl-5 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>; }; &cpu0 {