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[209.132.180.67]) by mx.google.com with ESMTP id x5si3535580pfk.335.2017.05.10.10.01.35; Wed, 10 May 2017 10:01:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753853AbdEJRBW (ORCPT + 25 others); Wed, 10 May 2017 13:01:22 -0400 Received: from mail-wm0-f46.google.com ([74.125.82.46]:33701 "EHLO mail-wm0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753465AbdEJRBR (ORCPT ); Wed, 10 May 2017 13:01:17 -0400 Received: by mail-wm0-f46.google.com with SMTP id n198so25259956wmg.0 for ; Wed, 10 May 2017 10:01:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bHvty5Fq/TkIBFIwnWu0LUjbm2nmRdM9MZR9Mc2Cvb8=; b=ISY6h0hgWmkY//OSXbqmDl+JVVfce/DOo39tx17iU01Wo0TXMHveeTN0RD7YbumjRb K+hCLxrWJ76GhAuSy0RXAWqbCUZueTDnk6N6xhqj8uWBMi5PEJx7U2Drump1uRiumzhi usBgnjSulQ5PgwCSad3SoAtB5VEHjqAR3z5V0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bHvty5Fq/TkIBFIwnWu0LUjbm2nmRdM9MZR9Mc2Cvb8=; b=XjrsnBi0BUmty6agTYz1MWfBkIdfsJR8P1xM5NtXl8iBug7Zrmrvq+rtF+/HlPQIsO rM4flgGUkZk/2LMmLdzyeCcfiLKJ9YTRyHecpmXe5fDZVvxiOfUWN8Gs47JgwNnZNe7O xAYuHHqpEvaiv0iYV7qb511Lo1dUKL/7AksP3vxuxslADdP6hPix0QVXlSZyf1zydlEF ahqpQBMJnpavvyWWEOMlNVK3BF5FGYWcBAfDHdVYmb+x8nClGK0Gulx4RXSoXk4WT5JR e/pgx4P6ukwoYl6EEhLMRdP3FJL2RvraBCfuXLrT+jhsjJGu5ReQAXZ9zil71YHXq7Br hBZA== X-Gm-Message-State: AODbwcCwVzhIPv6+ncfh463QpuPn/PujB4jWh6l0BG/4UsTqVLVQKGOM C7uL1yqsrN4dxRUR X-Received: by 10.28.178.201 with SMTP id b192mr3922320wmf.127.1494435676046; Wed, 10 May 2017 10:01:16 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id y60sm3438973wrb.39.2017.05.10.10.01.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 10 May 2017 10:01:13 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 384933E0355; Wed, 10 May 2017 18:02:01 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: christoffer.dall@linaro.org, marc.zyngier@arm.com Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, Zhichao Huang , =?utf-8?q?Alex_Benn=C3=A9e?= , Paolo Bonzini , =?utf-8?q?Radim_Kr=C4=8Dm?= =?utf-8?b?w6HFmQ==?= , Russell King , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v1 2/2] KVM: arm: rename pm_fake handler to trap_raz_wi Date: Wed, 10 May 2017 18:01:59 +0100 Message-Id: <20170510170200.13285-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170510170200.13285-1-alex.bennee@linaro.org> References: <20170510170200.13285-1-alex.bennee@linaro.org> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Zhichao Huang pm_fake doesn't quite describe what the handler does (ignoring writes and returning 0 for reads). As we're about to use it (a lot) in a different context, rename it with a (admitedly cryptic) name that make sense for all users. Signed-off-by: Zhichao Huang Reviewed-by: Alex Bennee Acked-by: Christoffer Dall Signed-off-by: Alex BennĂ©e --- arch/arm/kvm/coproc.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) -- 2.11.0 Acked-by: Marc Zyngier diff --git a/arch/arm/kvm/coproc.c b/arch/arm/kvm/coproc.c index b2053393bb1f..6919363ce7cc 100644 --- a/arch/arm/kvm/coproc.c +++ b/arch/arm/kvm/coproc.c @@ -260,7 +260,7 @@ static bool access_gic_sre(struct kvm_vcpu *vcpu, * must always support PMCCNTR (the cycle counter): we just RAZ/WI for * all PM registers, which doesn't crash the guest kernel at least. */ -static bool pm_fake(struct kvm_vcpu *vcpu, +static bool trap_raz_wi(struct kvm_vcpu *vcpu, const struct coproc_params *p, const struct coproc_reg *r) { @@ -270,19 +270,19 @@ static bool pm_fake(struct kvm_vcpu *vcpu, return read_zero(vcpu, p); } -#define access_pmcr pm_fake -#define access_pmcntenset pm_fake -#define access_pmcntenclr pm_fake -#define access_pmovsr pm_fake -#define access_pmselr pm_fake -#define access_pmceid0 pm_fake -#define access_pmceid1 pm_fake -#define access_pmccntr pm_fake -#define access_pmxevtyper pm_fake -#define access_pmxevcntr pm_fake -#define access_pmuserenr pm_fake -#define access_pmintenset pm_fake -#define access_pmintenclr pm_fake +#define access_pmcr trap_raz_wi +#define access_pmcntenset trap_raz_wi +#define access_pmcntenclr trap_raz_wi +#define access_pmovsr trap_raz_wi +#define access_pmselr trap_raz_wi +#define access_pmceid0 trap_raz_wi +#define access_pmceid1 trap_raz_wi +#define access_pmccntr trap_raz_wi +#define access_pmxevtyper trap_raz_wi +#define access_pmxevcntr trap_raz_wi +#define access_pmuserenr trap_raz_wi +#define access_pmintenset trap_raz_wi +#define access_pmintenclr trap_raz_wi /* Architected CP15 registers. * CRn denotes the primary register number, but is copied to the CRm in the @@ -527,7 +527,7 @@ static int kvm_handle_cp_64(struct kvm_vcpu *vcpu, struct kvm_run *run, return emulate_cp15(vcpu, ¶ms); /* raz_wi cp14 */ - (void)pm_fake(vcpu, ¶ms, NULL); + (void)trap_raz_wi(vcpu, ¶ms, NULL); /* handled */ kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu)); @@ -583,7 +583,7 @@ static int kvm_handle_cp_32(struct kvm_vcpu *vcpu, struct kvm_run *run, return emulate_cp15(vcpu, ¶ms); /* raz_wi cp14 */ - (void)pm_fake(vcpu, ¶ms, NULL); + (void)trap_raz_wi(vcpu, ¶ms, NULL); /* handled */ kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));