diff mbox series

[06/32] phy: sun4i-usb: add PHYCTL offset for H3 SoC

Message ID	20170410131823.26485-7-kishon@ti.com
State	New
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; From: Kishon Vijay Abraham I <kishon@ti.com> To: <gregkh@linuxfoundation.org> CC: <kishon@ti.com>, <linux-kernel@vger.kernel.org> Subject: [PATCH 06/32] phy: sun4i-usb: add PHYCTL offset for H3 SoC Date: Mon, 10 Apr 2017 18:47:57 +0530 Message-ID: <20170410131823.26485-7-kishon@ti.com> In-Reply-To: <20170410131823.26485-1-kishon@ti.com> References: <20170410131823.26485-1-kishon@ti.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk
Series	[01/32] mfd: exynos-lpass: Use common soc/exynos-regs-pmu.h header \| expand [01/32] mfd: exynos-lpass: Use common soc/exynos-regs-pmu.h header [02/32] phy: phy-exynos-pcie: make it explicitly non-modular [03/32] mfd: exynos-lpass: Use common soc/exynos-regs-pmu.h header [04/32] dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64 [05/32] phy: sun4i-usb: change PHYCTL register clearing code [06/32] phy: sun4i-usb: add PHYCTL offset for H3 SoC [07/32] phy: sun4i-usb: support automatically switch PHY0 route to MUSB/HCI [08/32] phy: meson8b-usb2: fix offsets for some of the registers [09/32] phy: exynos4: Remove duplicated defines of PHY register defines [10/32] phy: exynos5: Remove duplicated defines of PHY register defines [11/32] phy: exynos-mipi-video: Use consistent method to address phy registers [12/32] phy: exynos: Use one define for enable bit [13/32] phy: rockchip-inno-usb2: fix spelling mistake: "connecetd" -> "connected" [14/32] phy: rcar-gen3-usb2: fix implementation for runtime PM [15/32] phy: sun4i-usb: enable PHY0 dual route switching for A64 USB PHY [16/32] phy: phy-mt65xx-usb3: improve RX detection stable time [17/32] phy: phy-mt65xx-usb3: increase LFPS filter threshold [18/32] phy: phy-mt65xx-usb3: split SuperSpeed port into two ones [19/32] phy: phy-mt65xx-usb3: move clock from phy node into port nodes [20/32] phy: phy-mt65xx-usb3: add support for new version phy [21/32] phy: phy-mt65xx-usb3: disable 100uA extraction from SS port to HS port [22/32] dt-bindings: phy-mt65xx-usb: add support for new version phy [23/32] dt-bindings: phy-rockchip-inno-usb2: add assign clock property in usb2-phy node [24/32] dt-bindings: add DT bindings for usb2-phy grf [25/32] phy: rockchip-inno-usb2: add support of usb2-phy for rk3328 [26/32] dt-bindings: phy: Add support for QUSB2 phy [27/32] phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips [28/32] dt-bindings: phy: Add support for QMP phy [29/32] phy: qcom-qmp: new qmp phy driver for qcom-chipsets [30/32] phy: bcm-ns-usb3: split all writes into reg & val pairs [31/32] phy: rockchip-usb: Add vbus regulator support. [32/32] phy: qcom-qusb2: add NVMEM dependency

Commit Message

Kishon Vijay Abraham I April 10, 2017, 1:17 p.m. UTC

From: Icenowy Zheng <icenowy@aosc.xyz>


The config structure of H3 in phy-sun4i-usb driver have the PHYCTL
register offset missing.

Add it. From the BSP source code, we know that the offset should be
0x10.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

---
 drivers/phy/phy-sun4i-usb.c | 1 +
 1 file changed, 1 insertion(+)

-- 
2.11.0

diff mbox series

Patch

diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
index 62b4d25448c6..a650f283f6ff 100644
--- a/drivers/phy/phy-sun4i-usb.c
+++ b/drivers/phy/phy-sun4i-usb.c
@@ -821,6 +821,7 @@  static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
 	.num_phys = 4,
 	.type = sun8i_h3_phy,
 	.disc_thresh = 3,
+	.phyctl_offset = REG_PHYCTL_A33,
 	.dedicated_clocks = true,
 	.enable_pmu_unk1 = true,
 };