From patchwork Mon Apr 10 13:17:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 97133 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp1358630qgd; Mon, 10 Apr 2017 06:18:42 -0700 (PDT) X-Received: by 10.99.53.135 with SMTP id c129mr49984727pga.37.1491830322623; Mon, 10 Apr 2017 06:18:42 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y5si13569236pgi.411.2017.04.10.06.18.42; Mon, 10 Apr 2017 06:18:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753643AbdDJNSf (ORCPT + 24 others); Mon, 10 Apr 2017 09:18:35 -0400 Received: from lelnx194.ext.ti.com ([198.47.27.80]:57534 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752750AbdDJNSd (ORCPT ); Mon, 10 Apr 2017 09:18:33 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v3ADIWgR000889; Mon, 10 Apr 2017 08:18:32 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1491830312; bh=H62Dx8+hBdQTUdOFgZB7uDolNVAprh4youQK1YFd77s=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=dhUhUYOEjFFKaQjQZrhFam9OBQRgLI+7gQJSwdyCNKESRvQ9ZhxCHv9DbURGg245u 6tMlIo1XDKyK8aNplhQoAulp9U5rWKPb4HM+Hs+g8V4zwRhakyCRWIxNsgrcSnbUs0 6htEN2GVPKeb1l2+i+0SYYKlhAieEx0A1cxnmm00= Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v3ADIWHw020131; Mon, 10 Apr 2017 08:18:32 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.294.0; Mon, 10 Apr 2017 08:18:32 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v3ADIOLw032573; Mon, 10 Apr 2017 08:18:31 -0500 From: Kishon Vijay Abraham I To: CC: , Subject: [PATCH 04/32] dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64 Date: Mon, 10 Apr 2017 18:47:55 +0530 Message-ID: <20170410131823.26485-5-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170410131823.26485-1-kishon@ti.com> References: <20170410131823.26485-1-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Icenowy Zheng Allwinner H3/V3s/A64 SoCs have a special USB PHY0 that can route to two controllers: one is MUSB and the other is a EHCI/OHCI pair. When it's routed to EHCI/OHCI pair, it will needs a "pmu0" regs to tweak, like other EHCI/OHCI pairs in Allwinner SoCs. Add this to the binding of USB PHYs on Allwinner H3/V3s/A64. Signed-off-by: Icenowy Zheng Acked-by: Chen-Yu Tsai Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 1 + 1 file changed, 1 insertion(+) -- 2.11.0 diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt index e42334258185..005bc22938ff 100644 --- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt +++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt @@ -15,6 +15,7 @@ Required properties: - reg : a list of offset + length pairs - reg-names : * "phy_ctrl" + * "pmu0" for H3, V3s and A64 * "pmu1" * "pmu2" for sun4i, sun6i or sun7i - #phy-cells : from the generic phy bindings, must be 1