From patchwork Mon Apr 10 13:18:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 97147 Delivered-To: patch@linaro.org Received: by 10.182.246.10 with SMTP id xs10csp1353289obc; Mon, 10 Apr 2017 06:22:00 -0700 (PDT) X-Received: by 10.99.94.67 with SMTP id s64mr9992095pgb.71.1491830520805; Mon, 10 Apr 2017 06:22:00 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c66si13612019pfj.230.2017.04.10.06.22.00; Mon, 10 Apr 2017 06:22:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754093AbdDJNVT (ORCPT + 24 others); Mon, 10 Apr 2017 09:21:19 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:62001 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753969AbdDJNTW (ORCPT ); Mon, 10 Apr 2017 09:19:22 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v3ADJBVd008976; Mon, 10 Apr 2017 08:19:11 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1491830351; bh=r6/n/OM+3QtrIGIOTdTrj9bugApOTISti2C2zDnTP6o=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=MHAtb+exypJmv/+vzOOVN+JKLSDUNknjbk0bRKY3izvl6R85ATEhPRDyULLDfjnZX jJrKRha1bjON4GDdn7Jq5Sj4LbpH7IvigVuxn8wY79NQdTZiBUSTP8dauBUOBBooNA DdNS+6TivbgMtfDXB1yJGbbeCwEnAdw5SaxFslAs= Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v3ADJBUf020908; Mon, 10 Apr 2017 08:19:11 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.294.0; Mon, 10 Apr 2017 08:19:11 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v3ADIOMO032573; Mon, 10 Apr 2017 08:19:10 -0500 From: Kishon Vijay Abraham I To: CC: , Subject: [PATCH 30/32] phy: bcm-ns-usb3: split all writes into reg & val pairs Date: Mon, 10 Apr 2017 18:48:21 +0530 Message-ID: <20170410131823.26485-31-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170410131823.26485-1-kishon@ti.com> References: <20170410131823.26485-1-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Rafał Miłecki So far all the PHY initialization was implemented using some totally magic values. There was some pattern there but it wasn't clear what is it about. Thanks to the patch submitted by Broadcom: [PATCH 5/6] phy: Add USB3 PHY support for Broadcom NSP SoC and the upstream "iproc-mdio" driver we now know there is a MDIO bus underneath with PHY(s) and their registers. It allows us to clean the driver a bit by making all these values less magical. The next step is switching to using a proper MDIO layer. Signed-off-by: Rafał Miłecki Acked-by: Jon Mason Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/phy-bcm-ns-usb3.c | 69 ++++++++++++++++++++++++++++++------------- 1 file changed, 49 insertions(+), 20 deletions(-) -- 2.11.0 diff --git a/drivers/phy/phy-bcm-ns-usb3.c b/drivers/phy/phy-bcm-ns-usb3.c index f420fa4bebfc..22b5e7047fa6 100644 --- a/drivers/phy/phy-bcm-ns-usb3.c +++ b/drivers/phy/phy-bcm-ns-usb3.c @@ -2,6 +2,7 @@ * Broadcom Northstar USB 3.0 PHY Driver * * Copyright (C) 2016 Rafał Miłecki + * Copyright (C) 2016 Broadcom * * All magic values used for initialization (and related comments) were obtained * from Broadcom's SDK: @@ -23,6 +24,23 @@ #define BCM_NS_USB3_MII_MNG_TIMEOUT_US 1000 /* usecs */ +#define BCM_NS_USB3_PHY_BASE_ADDR_REG 0x1f +#define BCM_NS_USB3_PHY_PLL30_BLOCK 0x8000 +#define BCM_NS_USB3_PHY_TX_PMD_BLOCK 0x8040 +#define BCM_NS_USB3_PHY_PIPE_BLOCK 0x8060 + +/* Registers of PLL30 block */ +#define BCM_NS_USB3_PLL_CONTROL 0x01 +#define BCM_NS_USB3_PLLA_CONTROL0 0x0a +#define BCM_NS_USB3_PLLA_CONTROL1 0x0b + +/* Registers of TX PMD block */ +#define BCM_NS_USB3_TX_PMD_CONTROL1 0x01 + +/* Registers of PIPE block */ +#define BCM_NS_USB3_LFPS_CMP 0x02 +#define BCM_NS_USB3_LFPS_DEGLITCH 0x03 + enum bcm_ns_family { BCM_NS_UNKNOWN, BCM_NS_AX, @@ -76,8 +94,10 @@ static inline int bcm_ns_usb3_mii_mng_wait_idle(struct bcm_ns_usb3 *usb3) usecs_to_jiffies(BCM_NS_USB3_MII_MNG_TIMEOUT_US)); } -static int bcm_ns_usb3_mii_mng_write32(struct bcm_ns_usb3 *usb3, u32 value) +static int bcm_ns_usb3_mdio_phy_write(struct bcm_ns_usb3 *usb3, u16 reg, + u16 value) { + u32 tmp = 0; int err; err = bcm_ns_usb3_mii_mng_wait_idle(usb3); @@ -86,7 +106,11 @@ static int bcm_ns_usb3_mii_mng_write32(struct bcm_ns_usb3 *usb3, u32 value) return err; } - writel(value, usb3->ccb_mii + BCMA_CCB_MII_MNG_CMD_DATA); + /* TODO: Use a proper MDIO bus layer */ + tmp |= 0x58020000; /* Magic value for MDIO PHY write */ + tmp |= reg << 18; + tmp |= value; + writel(tmp, usb3->ccb_mii + BCMA_CCB_MII_MNG_CMD_DATA); return 0; } @@ -102,21 +126,22 @@ static int bcm_ns_usb3_phy_init_ns_bx(struct bcm_ns_usb3 *usb3) udelay(2); /* USB3 PLL Block */ - err = bcm_ns_usb3_mii_mng_write32(usb3, 0x587e8000); + err = bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PHY_BASE_ADDR_REG, + BCM_NS_USB3_PHY_PLL30_BLOCK); if (err < 0) return err; /* Assert Ana_Pllseq start */ - bcm_ns_usb3_mii_mng_write32(usb3, 0x58061000); + bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PLL_CONTROL, 0x1000); /* Assert CML Divider ratio to 26 */ - bcm_ns_usb3_mii_mng_write32(usb3, 0x582a6400); + bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PLLA_CONTROL0, 0x6400); /* Asserting PLL Reset */ - bcm_ns_usb3_mii_mng_write32(usb3, 0x582ec000); + bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PLLA_CONTROL1, 0xc000); /* Deaaserting PLL Reset */ - bcm_ns_usb3_mii_mng_write32(usb3, 0x582e8000); + bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PLLA_CONTROL1, 0x8000); /* Waiting MII Mgt interface idle */ bcm_ns_usb3_mii_mng_wait_idle(usb3); @@ -125,22 +150,24 @@ static int bcm_ns_usb3_phy_init_ns_bx(struct bcm_ns_usb3 *usb3) writel(0, usb3->dmp + BCMA_RESET_CTL); /* PLL frequency monitor enable */ - bcm_ns_usb3_mii_mng_write32(usb3, 0x58069000); + bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PLL_CONTROL, 0x9000); /* PIPE Block */ - bcm_ns_usb3_mii_mng_write32(usb3, 0x587e8060); + bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PHY_BASE_ADDR_REG, + BCM_NS_USB3_PHY_PIPE_BLOCK); /* CMPMAX & CMPMINTH setting */ - bcm_ns_usb3_mii_mng_write32(usb3, 0x580af30d); + bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_LFPS_CMP, 0xf30d); /* DEGLITCH MIN & MAX setting */ - bcm_ns_usb3_mii_mng_write32(usb3, 0x580e6302); + bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_LFPS_DEGLITCH, 0x6302); /* TXPMD block */ - bcm_ns_usb3_mii_mng_write32(usb3, 0x587e8040); + bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PHY_BASE_ADDR_REG, + BCM_NS_USB3_PHY_TX_PMD_BLOCK); /* Enabling SSC */ - bcm_ns_usb3_mii_mng_write32(usb3, 0x58061003); + bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_TX_PMD_CONTROL1, 0x1003); /* Waiting MII Mgt interface idle */ bcm_ns_usb3_mii_mng_wait_idle(usb3); @@ -159,22 +186,24 @@ static int bcm_ns_usb3_phy_init_ns_ax(struct bcm_ns_usb3 *usb3) udelay(2); /* PLL30 block */ - err = bcm_ns_usb3_mii_mng_write32(usb3, 0x587e8000); + err = bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PHY_BASE_ADDR_REG, + BCM_NS_USB3_PHY_PLL30_BLOCK); if (err < 0) return err; - bcm_ns_usb3_mii_mng_write32(usb3, 0x582a6400); + bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PLLA_CONTROL0, 0x6400); - bcm_ns_usb3_mii_mng_write32(usb3, 0x587e80e0); + bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PHY_BASE_ADDR_REG, 0x80e0); - bcm_ns_usb3_mii_mng_write32(usb3, 0x580a009c); + bcm_ns_usb3_mdio_phy_write(usb3, 0x02, 0x009c); /* Enable SSC */ - bcm_ns_usb3_mii_mng_write32(usb3, 0x587e8040); + bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PHY_BASE_ADDR_REG, + BCM_NS_USB3_PHY_TX_PMD_BLOCK); - bcm_ns_usb3_mii_mng_write32(usb3, 0x580a21d3); + bcm_ns_usb3_mdio_phy_write(usb3, 0x02, 0x21d3); - bcm_ns_usb3_mii_mng_write32(usb3, 0x58061003); + bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_TX_PMD_CONTROL1, 0x1003); /* Waiting MII Mgt interface idle */ bcm_ns_usb3_mii_mng_wait_idle(usb3);