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[24/32] dt-bindings: add DT bindings for usb2-phy grf

Message ID	20170410131823.26485-25-kishon@ti.com
State	Accepted
Commit	40544ba5911d9307372882d82377bd9526a11cea
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; From: Kishon Vijay Abraham I <kishon@ti.com> To: <gregkh@linuxfoundation.org> CC: <kishon@ti.com>, <linux-kernel@vger.kernel.org> Subject: [PATCH 24/32] dt-bindings: add DT bindings for usb2-phy grf Date: Mon, 10 Apr 2017 18:48:15 +0530 Message-ID: <20170410131823.26485-25-kishon@ti.com> In-Reply-To: <20170410131823.26485-1-kishon@ti.com> References: <20170410131823.26485-1-kishon@ti.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk
Series	[01/32] mfd: exynos-lpass: Use common soc/exynos-regs-pmu.h header \| expand [01/32] mfd: exynos-lpass: Use common soc/exynos-regs-pmu.h header [02/32] phy: phy-exynos-pcie: make it explicitly non-modular [03/32] mfd: exynos-lpass: Use common soc/exynos-regs-pmu.h header [04/32] dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64 [05/32] phy: sun4i-usb: change PHYCTL register clearing code [06/32] phy: sun4i-usb: add PHYCTL offset for H3 SoC [07/32] phy: sun4i-usb: support automatically switch PHY0 route to MUSB/HCI [08/32] phy: meson8b-usb2: fix offsets for some of the registers [09/32] phy: exynos4: Remove duplicated defines of PHY register defines [10/32] phy: exynos5: Remove duplicated defines of PHY register defines [11/32] phy: exynos-mipi-video: Use consistent method to address phy registers [12/32] phy: exynos: Use one define for enable bit [13/32] phy: rockchip-inno-usb2: fix spelling mistake: "connecetd" -> "connected" [14/32] phy: rcar-gen3-usb2: fix implementation for runtime PM [15/32] phy: sun4i-usb: enable PHY0 dual route switching for A64 USB PHY [16/32] phy: phy-mt65xx-usb3: improve RX detection stable time [17/32] phy: phy-mt65xx-usb3: increase LFPS filter threshold [18/32] phy: phy-mt65xx-usb3: split SuperSpeed port into two ones [19/32] phy: phy-mt65xx-usb3: move clock from phy node into port nodes [20/32] phy: phy-mt65xx-usb3: add support for new version phy [21/32] phy: phy-mt65xx-usb3: disable 100uA extraction from SS port to HS port [22/32] dt-bindings: phy-mt65xx-usb: add support for new version phy [23/32] dt-bindings: phy-rockchip-inno-usb2: add assign clock property in usb2-phy node [24/32] dt-bindings: add DT bindings for usb2-phy grf [25/32] phy: rockchip-inno-usb2: add support of usb2-phy for rk3328 [26/32] dt-bindings: phy: Add support for QUSB2 phy [27/32] phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips [28/32] dt-bindings: phy: Add support for QMP phy [29/32] phy: qcom-qmp: new qmp phy driver for qcom-chipsets [30/32] phy: bcm-ns-usb3: split all writes into reg & val pairs [31/32] phy: rockchip-usb: Add vbus regulator support. [32/32] phy: qcom-qusb2: add NVMEM dependency

Commit Message

Kishon Vijay Abraham I April 10, 2017, 1:18 p.m. UTC

From: Meng Dongyang <daniel.meng@rock-chips.com>


Adds the device tree bindings description for usb2-phy grf
of RK3328 platform.

Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>

Reviewed-by: Heiko Stuebner <heiko@sntech.de>

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

---
 Documentation/devicetree/bindings/soc/rockchip/grf.txt | 4 ++++
 1 file changed, 4 insertions(+)

-- 
2.11.0

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Patch

diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.txt b/Documentation/devicetree/bindings/soc/rockchip/grf.txt
index a0685c209218..13ec0992de0f 100644
--- a/Documentation/devicetree/bindings/soc/rockchip/grf.txt
+++ b/Documentation/devicetree/bindings/soc/rockchip/grf.txt
@@ -8,6 +8,8 @@  From RK3368 SoCs, the GRF is divided into two sections,
 - SGRF, used for general secure system,
 - PMUGRF, used for always on system
 
+On RK3328 SoCs, the GRF adds a section for USB2PHYGRF,
+
 Required Properties:
 
 - compatible: GRF should be one of the following:
@@ -23,6 +25,8 @@  Required Properties:
    - "rockchip,rk3399-pmugrf", "syscon": for rk3399
 - compatible: SGRF should be one of the following
    - "rockchip,rk3288-sgrf", "syscon": for rk3288
+- compatible: USB2PHYGRF should be one of the followings
+   - "rockchip,rk3328-usb2phy-grf", "syscon": for rk3328
 - reg: physical base address of the controller and length of memory mapped
   region.