From patchwork Mon Apr 10 13:18:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 97152 Delivered-To: patch@linaro.org Received: by 10.182.246.10 with SMTP id xs10csp1353564obc; Mon, 10 Apr 2017 06:22:42 -0700 (PDT) X-Received: by 10.99.174.9 with SMTP id q9mr54212620pgf.232.1491830562039; Mon, 10 Apr 2017 06:22:42 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q3si13659505plb.23.2017.04.10.06.22.41; Mon, 10 Apr 2017 06:22:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753914AbdDJNTR (ORCPT + 24 others); Mon, 10 Apr 2017 09:19:17 -0400 Received: from lelnx194.ext.ti.com ([198.47.27.80]:57562 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753896AbdDJNTN (ORCPT ); Mon, 10 Apr 2017 09:19:13 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v3ADIwHo000955; Mon, 10 Apr 2017 08:18:58 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1491830338; bh=dG/W0c4+1ArpvNpKVnMpCPGxs9HosYmSgXkJSsvB5qo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=MYlNgzfJf2M7SrKbT/MU+5IRwl0fBY2+5Bm6lfD4xwiK9YIMOwSrG3DvNrKko9/Qy rSH59Rg85zeAVES2s9nn+y4M+xP1VILEkFIj/nlsEwqPo9D069cdoOK2SoAl+Zdl8O ILoGeNDaQcciUpvPX9s3AY1YY9klUI3UkpUhD8gs= Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v3ADIwg6027562; Mon, 10 Apr 2017 08:18:58 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.294.0; Mon, 10 Apr 2017 08:18:57 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v3ADIOMF032573; Mon, 10 Apr 2017 08:18:56 -0500 From: Kishon Vijay Abraham I To: CC: , Subject: [PATCH 21/32] phy: phy-mt65xx-usb3: disable 100uA extraction from SS port to HS port Date: Mon, 10 Apr 2017 18:48:12 +0530 Message-ID: <20170410131823.26485-22-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170410131823.26485-1-kishon@ti.com> References: <20170410131823.26485-1-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Chunfeng Yun There will be a problem if SS port is diasbled and HS port extracts 100uA from SS port, so disable extract 100uA from SS port in the case, when disable it, PA0_RG_USB20_INTR_EN should be set, otherwise HS port only works on LS. Signed-off-by: Chunfeng Yun Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/phy-mt65xx-usb3.c | 24 ++++++++++-------------- 1 file changed, 10 insertions(+), 14 deletions(-) -- 2.11.0 diff --git a/drivers/phy/phy-mt65xx-usb3.c b/drivers/phy/phy-mt65xx-usb3.c index e99788babfb9..59b110f795c3 100644 --- a/drivers/phy/phy-mt65xx-usb3.c +++ b/drivers/phy/phy-mt65xx-usb3.c @@ -46,6 +46,7 @@ #define U3P_USBPHYACR0 0x000 #define PA0_RG_U2PLL_FORCE_ON BIT(15) +#define PA0_RG_USB20_INTR_EN BIT(5) #define U3P_USBPHYACR2 0x008 #define PA2_RG_SIF_U2PLL_FORCE_EN BIT(18) @@ -339,6 +340,15 @@ static void phy_instance_init(struct mt65xx_u3phy *u3phy, tmp &= ~P2C_RG_UART_EN; writel(tmp, com + U3P_U2PHYDTM1); + tmp = readl(com + U3P_USBPHYACR0); + tmp |= PA0_RG_USB20_INTR_EN; + writel(tmp, com + U3P_USBPHYACR0); + + /* disable switch 100uA current to SSUSB */ + tmp = readl(com + U3P_USBPHYACR5); + tmp &= ~PA5_RG_U2_HS_100U_U3_EN; + writel(tmp, com + U3P_USBPHYACR5); + if (!index) { tmp = readl(com + U3P_U2PHYACR4); tmp &= ~P2C_U2_GPIO_CTR_MSK; @@ -393,13 +403,6 @@ static void phy_instance_power_on(struct mt65xx_u3phy *u3phy, tmp |= PA6_RG_U2_OTG_VBUSCMP_EN; writel(tmp, com + U3P_USBPHYACR6); - if (!index) { - /* switch 100uA current to SSUSB */ - tmp = readl(com + U3P_USBPHYACR5); - tmp |= PA5_RG_U2_HS_100U_U3_EN; - writel(tmp, com + U3P_USBPHYACR5); - } - tmp = readl(com + U3P_U2PHYDTM1); tmp |= P2C_RG_VBUSVALID | P2C_RG_AVALID; tmp &= ~P2C_RG_SESSEND; @@ -435,13 +438,6 @@ static void phy_instance_power_off(struct mt65xx_u3phy *u3phy, tmp &= ~PA6_RG_U2_OTG_VBUSCMP_EN; writel(tmp, com + U3P_USBPHYACR6); - if (!index) { - /* switch 100uA current back to USB2.0 */ - tmp = readl(com + U3P_USBPHYACR5); - tmp &= ~PA5_RG_U2_HS_100U_U3_EN; - writel(tmp, com + U3P_USBPHYACR5); - } - /* let suspendm=0, set utmi into analog power down */ tmp = readl(com + U3P_U2PHYDTM0); tmp &= ~P2C_RG_SUSPENDM;