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[209.132.180.67]) by mx.google.com with ESMTP id q3si13659505plb.23.2017.04.10.06.22.21; Mon, 10 Apr 2017 06:22:21 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754101AbdDJNVx (ORCPT + 24 others); Mon, 10 Apr 2017 09:21:53 -0400 Received: from fllnx210.ext.ti.com ([198.47.19.17]:11372 "EHLO fllnx210.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753949AbdDJNTV (ORCPT ); Mon, 10 Apr 2017 09:19:21 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id v3ADItC0025971; Mon, 10 Apr 2017 08:18:55 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1491830335; bh=nfY6Vi/gsRrSVUkdTDSOEK+uhb5QvRA07OpfUgahxfw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=LyypTAJKpTyxjVH5qm6Y8nX5RQmzGSNUL7GPev3ziJz3yrNt1m1VvbrJ4X6NwZKY0 ETEkle7FsRN3dxPNQPhS6dQkEwSb154Gu/e3LAh2eSYnBcvRqne85Kx7WFwA6yKCZX YPoNkoOyTRdIAQ6JvE8YBAUHfUK8AvzM8kOpB7QA= Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v3ADItkL027542; Mon, 10 Apr 2017 08:18:55 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.294.0; Mon, 10 Apr 2017 08:18:54 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v3ADIOMD032573; Mon, 10 Apr 2017 08:18:53 -0500 From: Kishon Vijay Abraham I To: CC: , Subject: [PATCH 19/32] phy: phy-mt65xx-usb3: move clock from phy node into port nodes Date: Mon, 10 Apr 2017 18:48:10 +0530 Message-ID: <20170410131823.26485-20-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170410131823.26485-1-kishon@ti.com> References: <20170410131823.26485-1-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Chunfeng Yun each port has its own reference clock, the HighSpeed port is 48M, and the SuperSpeed port is usually 26M, put them into port node for flexibility, this can close clock if the port is not used. Signed-off-by: Chunfeng Yun Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/phy-mt65xx-usb3.c | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) -- 2.11.0 diff --git a/drivers/phy/phy-mt65xx-usb3.c b/drivers/phy/phy-mt65xx-usb3.c index 7fff482f498d..34035721cf62 100644 --- a/drivers/phy/phy-mt65xx-usb3.c +++ b/drivers/phy/phy-mt65xx-usb3.c @@ -153,6 +153,7 @@ struct mt65xx_phy_pdata { struct mt65xx_phy_instance { struct phy *phy; void __iomem *port_base; + struct clk *ref_clk; /* reference clock of anolog phy */ u32 index; u8 type; }; @@ -160,6 +161,7 @@ struct mt65xx_phy_instance { struct mt65xx_u3phy { struct device *dev; void __iomem *sif_base; /* only shared sif */ + /* deprecated, use @ref_clk instead in phy instance */ struct clk *u3phya_ref; /* reference clock of usb3 anolog phy */ const struct mt65xx_phy_pdata *pdata; struct mt65xx_phy_instance **phys; @@ -455,6 +457,12 @@ static int mt65xx_phy_init(struct phy *phy) return ret; } + ret = clk_prepare_enable(instance->ref_clk); + if (ret) { + dev_err(u3phy->dev, "failed to enable ref_clk\n"); + return ret; + } + if (instance->type == PHY_TYPE_USB2) phy_instance_init(u3phy, instance); else @@ -494,6 +502,7 @@ static int mt65xx_phy_exit(struct phy *phy) if (instance->type == PHY_TYPE_USB2) phy_instance_exit(u3phy, instance); + clk_disable_unprepare(instance->ref_clk); clk_disable_unprepare(u3phy->u3phya_ref); return 0; } @@ -594,10 +603,13 @@ static int mt65xx_u3phy_probe(struct platform_device *pdev) return PTR_ERR(u3phy->sif_base); } + /* it's deprecated, make it optional for backward compatibility */ u3phy->u3phya_ref = devm_clk_get(dev, "u3phya_ref"); if (IS_ERR(u3phy->u3phya_ref)) { - dev_err(dev, "error to get u3phya_ref\n"); - return PTR_ERR(u3phy->u3phya_ref); + if (PTR_ERR(u3phy->u3phya_ref) == -EPROBE_DEFER) + return -EPROBE_DEFER; + + u3phy->u3phya_ref = NULL; } port = 0; @@ -638,6 +650,17 @@ static int mt65xx_u3phy_probe(struct platform_device *pdev) instance->index = port; phy_set_drvdata(phy, instance); port++; + + /* if deprecated clock is provided, ignore instance's one */ + if (u3phy->u3phya_ref) + continue; + + instance->ref_clk = devm_clk_get(&phy->dev, "ref"); + if (IS_ERR(instance->ref_clk)) { + dev_err(dev, "failed to get ref_clk(id-%d)\n", port); + retval = PTR_ERR(instance->ref_clk); + goto put_child; + } } provider = devm_of_phy_provider_register(dev, mt65xx_phy_xlate);