From patchwork Sat Apr 1 11:03:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Salil Mehta X-Patchwork-Id: 96541 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp1115096qgd; Sat, 1 Apr 2017 04:05:10 -0700 (PDT) X-Received: by 10.84.222.131 with SMTP id x3mr8655351pls.184.1491044710537; Sat, 01 Apr 2017 04:05:10 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s26si7892132pfk.332.2017.04.01.04.05.10; Sat, 01 Apr 2017 04:05:10 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752159AbdDALFJ (ORCPT + 21 others); Sat, 1 Apr 2017 07:05:09 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:5297 "EHLO dggrg01-dlp.huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1752034AbdDALFG (ORCPT ); Sat, 1 Apr 2017 07:05:06 -0400 Received: from 172.30.72.54 (EHLO DGGEML403-HUB.china.huawei.com) ([172.30.72.54]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id ALX13129; Sat, 01 Apr 2017 19:05:03 +0800 (CST) Received: from S00293818-DELL1.china.huawei.com (10.203.181.152) by DGGEML403-HUB.china.huawei.com (10.3.17.33) with Microsoft SMTP Server id 14.3.301.0; Sat, 1 Apr 2017 19:04:54 +0800 From: Salil Mehta To: CC: , , , , , , lipeng , JinchuanTian Subject: [PATCH V4 net-next 02/18] net: hns: Modify GMAC init TX threshold value Date: Sat, 1 Apr 2017 12:03:32 +0100 Message-ID: <20170401110348.15908-3-salil.mehta@huawei.com> X-Mailer: git-send-email 2.8.3 In-Reply-To: <20170401110348.15908-1-salil.mehta@huawei.com> References: <20170401110348.15908-1-salil.mehta@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.181.152] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020203.58DF895F.0147, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 72e9b69997208a2c5323aa4d399e1224 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: lipeng This patch reduces GMAC TX threshold value to avoid gmac hang-up with speed 100M/duplex half. Signed-off-by: lipeng Signed-off-by: JinchuanTian Reviewed-by: Yisen Zhuang Signed-off-by: Salil Mehta --- drivers/net/ethernet/hisilicon/hns/hns_dsaf_gmac.c | 6 ++++++ drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h | 4 ++++ 2 files changed, 10 insertions(+) -- 2.7.4 diff --git a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_gmac.c b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_gmac.c index 3382441..a8dbe00 100644 --- a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_gmac.c +++ b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_gmac.c @@ -325,6 +325,12 @@ static void hns_gmac_init(void *mac_drv) hns_gmac_tx_loop_pkt_dis(mac_drv); if (drv->mac_cb->mac_type == HNAE_PORT_DEBUG) hns_gmac_set_uc_match(mac_drv, 0); + + /* reduce gmac tx water line to avoid gmac hang-up + * in speed 100M and duplex half. + */ + dsaf_set_dev_field(drv, GMAC_TX_WATER_LINE_REG, GMAC_TX_WATER_LINE_MASK, + GMAC_TX_WATER_LINE_SHIFT, 8); } void hns_gmac_update_stats(void *mac_drv) diff --git a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h index 8fa18fc..4b8af68 100644 --- a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h +++ b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h @@ -466,6 +466,7 @@ #define GMAC_DUPLEX_TYPE_REG 0x0008UL #define GMAC_FD_FC_TYPE_REG 0x000CUL +#define GMAC_TX_WATER_LINE_REG 0x0010UL #define GMAC_FC_TX_TIMER_REG 0x001CUL #define GMAC_FD_FC_ADDR_LOW_REG 0x0020UL #define GMAC_FD_FC_ADDR_HIGH_REG 0x0024UL @@ -912,6 +913,9 @@ #define GMAC_DUPLEX_TYPE_B 0 +#define GMAC_TX_WATER_LINE_MASK ((1UL << 8) - 1) +#define GMAC_TX_WATER_LINE_SHIFT 0 + #define GMAC_FC_TX_TIMER_S 0 #define GMAC_FC_TX_TIMER_M 0xffff