From patchwork Fri Mar 31 11:20:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Salil Mehta X-Patchwork-Id: 96364 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp677358qgd; Fri, 31 Mar 2017 04:22:50 -0700 (PDT) X-Received: by 10.98.34.73 with SMTP id i70mr2365936pfi.248.1490959370886; Fri, 31 Mar 2017 04:22:50 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l2si4920377pga.406.2017.03.31.04.22.50; Fri, 31 Mar 2017 04:22:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933372AbdCaLWm (ORCPT + 21 others); Fri, 31 Mar 2017 07:22:42 -0400 Received: from szxga03-in.huawei.com ([45.249.212.189]:4941 "EHLO dggrg03-dlp.huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S932802AbdCaLWf (ORCPT ); Fri, 31 Mar 2017 07:22:35 -0400 Received: from 172.30.72.55 (EHLO DGGEML404-HUB.china.huawei.com) ([172.30.72.55]) by dggrg03-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AKY89336; Fri, 31 Mar 2017 19:22:22 +0800 (CST) Received: from S00293818-DELL1.china.huawei.com (10.203.181.152) by DGGEML404-HUB.china.huawei.com (10.3.17.39) with Microsoft SMTP Server id 14.3.301.0; Fri, 31 Mar 2017 19:22:13 +0800 From: Salil Mehta To: CC: , , , , , , Kejian Yan Subject: [PATCH V2 net-next 16/18] net: hns: Adjust the SBM module buffer threshold Date: Fri, 31 Mar 2017 12:20:30 +0100 Message-ID: <20170331112032.4692-17-salil.mehta@huawei.com> X-Mailer: git-send-email 2.8.3 In-Reply-To: <20170331112032.4692-1-salil.mehta@huawei.com> References: <20170331112032.4692-1-salil.mehta@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.181.152] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020205.58DE3BEF.0037, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 097c41cdd05ee36db9296af8ae8f9960 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Kejian Yan HNS needs SMB Buffers to store at least two packets after sending pause frame because of the link delay. The MTU of HNS is 9728. As the processor user manual described, the SBM buffer threshold should be modified. Reported-by: Ping Zhang Signed-off-by: Kejian Yan Reviewed-by: Salil Mehta Signed-off-by: Salil Mehta --- drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.7.4 diff --git a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c index abd8aec..d07b4fe 100644 --- a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c +++ b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c @@ -510,10 +510,10 @@ static void hns_dsafv2_sbm_bp_wl_cfg(struct dsaf_device *dsaf_dev) o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG3_SET_BUF_NUM_NO_PFC_M, - DSAFV2_SBM_CFG3_SET_BUF_NUM_NO_PFC_S, 48); + DSAFV2_SBM_CFG3_SET_BUF_NUM_NO_PFC_S, 55); dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M, - DSAFV2_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S, 80); + DSAFV2_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S, 110); dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); /* for no enable pfc mode */ @@ -521,10 +521,10 @@ static void hns_dsafv2_sbm_bp_wl_cfg(struct dsaf_device *dsaf_dev) o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG4_SET_BUF_NUM_NO_PFC_M, - DSAFV2_SBM_CFG4_SET_BUF_NUM_NO_PFC_S, 192); + DSAFV2_SBM_CFG4_SET_BUF_NUM_NO_PFC_S, 128); dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG4_RESET_BUF_NUM_NO_PFC_M, - DSAFV2_SBM_CFG4_RESET_BUF_NUM_NO_PFC_S, 240); + DSAFV2_SBM_CFG4_RESET_BUF_NUM_NO_PFC_S, 192); dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); }