From patchwork Mon Mar 13 13:43:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 95232 Delivered-To: patch@linaro.org Received: by 10.140.82.71 with SMTP id g65csp1178153qgd; Mon, 13 Mar 2017 06:45:22 -0700 (PDT) X-Received: by 10.98.112.134 with SMTP id l128mr37436369pfc.81.1489412722195; Mon, 13 Mar 2017 06:45:22 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b14si11468561pge.221.2017.03.13.06.45.21; Mon, 13 Mar 2017 06:45:22 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752183AbdCMNpF (ORCPT + 25 others); Mon, 13 Mar 2017 09:45:05 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:35787 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752748AbdCMNo2 (ORCPT ); Mon, 13 Mar 2017 09:44:28 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v2DDhgQl025489; Mon, 13 Mar 2017 08:43:42 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1489412622; bh=Nmg0DqhHaYoPPmmZsy4VXol2d3v8ZUeWJftsvQrVWv0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=dESMdUsgeIbINBwtf/lpKYemh+3kAadJVSR8m20+hjKQZ/rthiibB09AAe9NTeYDG W9Ahr9Z4Veawphd/gxfm2WVfX2Y/m8rjRnvpfc+/NfaK7yxDLGnnGuDRODHW6NvgPb Yz0pPPtlQ4f+CVsOWXyP+dT7U56yWS5lVLtAArjc= Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v2DDhg3k019297; Mon, 13 Mar 2017 08:43:42 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.294.0; Mon, 13 Mar 2017 08:43:41 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v2DDhZvj017427; Mon, 13 Mar 2017 08:43:39 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Joao Pinto , Niklas Cassel , , , , CC: , Subject: [PATCH v4 1/7] PCI: dwc: designware: Add new *ops* for cpu addr fixup Date: Mon, 13 Mar 2017 19:13:22 +0530 Message-ID: <20170313134328.1588-2-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170313134328.1588-1-kishon@ti.com> References: <20170313134328.1588-1-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Some platforms (like dra7xx) require only the least 28 bits of the corresponding 32 bit CPU address to be programmed in the address translation unit. This modified address is stored in io_base/mem_base/ cfg0_base/cfg1_base in dra7xx_pcie_host_init. While this is okay for host mode where the address range is fixed, device mode requires different addresses to be programmed based on the host buffer address. Add a new ops to get the least 28 bits of the corresponding 32 bit CPU address and invoke it before programming the address translation unit. Acked-by: Joao Pinto Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/dwc/pcie-designware.c | 3 +++ drivers/pci/dwc/pcie-designware.h | 1 + 2 files changed, 4 insertions(+) -- 2.11.0 diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c index 7e1fb7d6643c..3eaf3ccdc118 100644 --- a/drivers/pci/dwc/pcie-designware.c +++ b/drivers/pci/dwc/pcie-designware.c @@ -97,6 +97,9 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, { u32 retries, val; + if (pci->ops->cpu_addr_fixup) + cpu_addr = pci->ops->cpu_addr_fixup(cpu_addr); + if (pci->iatu_unroll_enabled) { dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE, lower_32_bits(cpu_addr)); diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h index cd3b8713fe50..8f3dcb2b099b 100644 --- a/drivers/pci/dwc/pcie-designware.h +++ b/drivers/pci/dwc/pcie-designware.h @@ -143,6 +143,7 @@ struct pcie_port { }; struct dw_pcie_ops { + u64 (*cpu_addr_fixup)(u64 cpu_addr); u32 (*readl_dbi)(struct dw_pcie *pcie, u32 reg); void (*writel_dbi)(struct dw_pcie *pcie, u32 reg, u32 val); int (*link_up)(struct dw_pcie *pcie);