From patchwork Mon Jan 2 16:37:15 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Quentin Schulz X-Patchwork-Id: 89545 Delivered-To: patch@linaro.org Received: by 10.140.20.101 with SMTP id 92csp7663188qgi; Mon, 2 Jan 2017 08:42:56 -0800 (PST) X-Received: by 10.84.217.216 with SMTP id d24mr127032515plj.101.1483375376321; Mon, 02 Jan 2017 08:42:56 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t4si46854673pgb.161.2017.01.02.08.42.55; Mon, 02 Jan 2017 08:42:56 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933647AbdABQjs (ORCPT + 25 others); Mon, 2 Jan 2017 11:39:48 -0500 Received: from mail.free-electrons.com ([62.4.15.54]:42813 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933466AbdABQiF (ORCPT ); Mon, 2 Jan 2017 11:38:05 -0500 Received: by mail.free-electrons.com (Postfix, from userid 110) id 28CD220773; Mon, 2 Jan 2017 17:38:06 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from qschulz.home (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id AC0D3206A8; Mon, 2 Jan 2017 17:38:05 +0100 (CET) From: Quentin Schulz To: jic23@kernel.org, knaack.h@gmx.de, lars@metafoo.de, pmeerw@pmeerw.net, robh+dt@kernel.org, mark.rutland@arm.com, wens@csie.org, sre@kernel.org, linux@armlinux.org.uk, maxime.ripard@free-electrons.com, lee.jones@linaro.org Cc: Quentin Schulz , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, thomas.petazzoni@free-electrons.com, icenowy@aosc.xyz, bonbons@linux-vserver.org Subject: [PATCH 15/22] mfd: axp20x: add CHRG_CTRL1 to writeable regs for AXP20X/AXP22X Date: Mon, 2 Jan 2017 17:37:15 +0100 Message-Id: <20170102163723.7939-16-quentin.schulz@free-electrons.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170102163723.7939-1-quentin.schulz@free-electrons.com> References: <20170102163723.7939-1-quentin.schulz@free-electrons.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The CHR_CTRL1 register is made of 7 read-write bits with one being used to set the target voltage for battery charging. This adds the CHRG_CTRL1 register to the list of writeable registers for AXP20X and AXP22X PMICs. Signed-off-by: Quentin Schulz --- drivers/mfd/axp20x.c | 2 ++ 1 file changed, 2 insertions(+) -- 2.9.3 diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c index 65c57d0..19bdba3 100644 --- a/drivers/mfd/axp20x.c +++ b/drivers/mfd/axp20x.c @@ -66,6 +66,7 @@ static const struct regmap_access_table axp152_volatile_table = { static const struct regmap_range axp20x_writeable_ranges[] = { regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ5_STATE), regmap_reg_range(AXP20X_VBUS_IPSOUT_MGMT, AXP20X_VBUS_IPSOUT_MGMT), + regmap_reg_range(AXP20X_CHRG_CTRL1, AXP20X_CHRG_CTRL1), regmap_reg_range(AXP20X_DCDC_MODE, AXP20X_FG_RES), regmap_reg_range(AXP20X_RDC_H, AXP20X_OCV(AXP20X_OCV_MAX)), }; @@ -94,6 +95,7 @@ static const struct regmap_access_table axp20x_volatile_table = { static const struct regmap_range axp22x_writeable_ranges[] = { regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ5_STATE), regmap_reg_range(AXP20X_VBUS_IPSOUT_MGMT, AXP20X_VBUS_IPSOUT_MGMT), + regmap_reg_range(AXP20X_CHRG_CTRL1, AXP20X_CHRG_CTRL1), regmap_reg_range(AXP20X_DCDC_MODE, AXP22X_BATLOW_THRES1), };