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([78.42.132.4]) by mrelayeu.kundenserver.de (mreue103) with ESMTPA (Nemesis) id 0Lsw94-1bA2KW0fso-012VGy; Thu, 25 Aug 2016 16:43:22 +0200 From: Arnd Bergmann To: Russell King Cc: linux-arm-kernel@lists.infradead.org, Arnd Bergmann , Nicolas Pitre , "David S. Miller" , Robert Jarzmik , Yoshinori Sato , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH] smc91x: remove ARM hack for unaligned 16-bit writes Date: Thu, 25 Aug 2016 16:43:04 +0200 Message-Id: <20160825144314.1850730-1-arnd@arndb.de> X-Mailer: git-send-email 2.9.0 X-Provags-ID: V03:K0:yd3phDcsIv1KdYx7Pv/3vvXtDKuHbNUMVEp1ZYQ8X6l0+p0MQcL dkrRv+bnfxYyK45+OumsfflKQ4F8QScQ+hCWxeAyvTkmfES2zOj9cgsqZBozCfaEhYGxsWb EdAs6S2jBqdgjvDat7GMptBXsSYEatb0jJyYDwAECbmRYN7ILSBIjCHHA8mTpITLcUa508I gXsFz7gBcT7ClPREOFHJQ== X-UI-Out-Filterresults: notjunk:1; V01:K0:uwVyqq/r18c=:2HOfJWtXQEFkU6T2UFHRCe jOsolWhbYWxGWnDAMruZiNDiMkNzz66bCjONARjhFj/8isb7auJ6CWzyHwXK4rNHTg/J88056 SpQp3aIp121CsaruXslo1sFJeXLHfsUdnVp1zcaAH/X+kkE0Soe9v15e++HRX2fijK/lRCeMU VnEb8U9WQbU0oiTnqznlIyaGEUeioQZ0fd/E3bjlGsNu96+uf395c41qs59LaALOrEK19LP/x ZY9lDVFhumQSjoHYLbC6sEl5Wq0qDAFDdTt0FSgob5eaCsqN1bgL3eRH8go+WEGavZjbop+ni QlLKrs+L386TbWGZ3xeWjlH2oTqK48HVRhkG/2qZD1On5/jqQs5YlvPJalpN0sqXF3pLzgHHx 6YPddQaF414Q4GwV4QXlT8plDFryBURZB7uZIdLhAl+hx87+ryw4K3rS4cdreHMuN4U6xS/WD Kj+edEXykkelsZxQ3jhmCp8yHGvfg19pQ23syzkvHVnep/mecfdyP1tyu8B5Z3nRo3uzoqARb s1X/yXkMG1mdnlfv5OqO1KqC8tlomRFOvU8oTkh6nUdQ+haepVGgMJEFpGsMXxmHHZvvjcUhB za1Yei++DXe1TEJGV+Ml8ELpr8nipxsXXXc37dPM867Bobgk9PlZAdpU/DyZjt9pKUvrmEZPV qf2iYZN1Y/s+5XHFbLbYbpDgzDauLe1jVsREqiGGqUpWcVgVuotZKFwU6mMKgxWQfk6A= Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The ARM specific I/O operations are almost the same as the generic ones, with the exception of the SMC_outw macro that works around a problem of some platforms that cannot write to 16-bit registers at an address that is not 32-bit aligned. By inspection, I found that this is handled already in the register abstractions for almost all cases, the exceptions being SMC_SET_MAC_ADDR() and SMC_SET_MCAST(). I assume that all platforms that require the hack for the other registers also need it here, so the ones listed explictly here are the only ones that work correctly, while the other ones either don't need the hack at all, or they will set an incorrect MAC address (which can often go unnoticed). This changes the two macros that set the unaligned registers to use 32-bit writes if possible, which should do the right thing in all combinations. The ARM specific SMC_outw gets removed as a consequence. The only difference between the ARM behavior and the default is the selection of the LED settings. The fact that we have different defaults based on the CPU architectures here is a bit suspicious, but probably harmless, and I have no plan of touching that. Signed-off-by: Arnd Bergmann --- drivers/net/ethernet/smsc/smc91x.h | 50 +++++++++++++++++++++++--------------- 1 file changed, 30 insertions(+), 20 deletions(-) While this patch fixes one bug on Neponset, it probably doesn't address the one that Russell ran into first, so this is for review only for now, until the remaining problem(s) have been worked out. -- 2.9.0 diff --git a/drivers/net/ethernet/smsc/smc91x.h b/drivers/net/ethernet/smsc/smc91x.h index 22333477d0b5..908473d9ede0 100644 --- a/drivers/net/ethernet/smsc/smc91x.h +++ b/drivers/net/ethernet/smsc/smc91x.h @@ -58,6 +58,7 @@ #define SMC_inw(a, r) readw((a) + (r)) #define SMC_inl(a, r) readl((a) + (r)) #define SMC_outb(v, a, r) writeb(v, (a) + (r)) +#define SMC_outw(v, a, r) writew(v, (a) + (r)) #define SMC_outl(v, a, r) writel(v, (a) + (r)) #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) @@ -65,19 +66,6 @@ #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) #define SMC_IRQ_FLAGS (-1) /* from resource */ -/* We actually can't write halfwords properly if not word aligned */ -static inline void SMC_outw(u16 val, void __iomem *ioaddr, int reg) -{ - if ((machine_is_mainstone() || machine_is_stargate2() || - machine_is_pxa_idp()) && reg & 2) { - unsigned int v = val << 16; - v |= readl(ioaddr + (reg & ~2)) & 0xffff; - writel(v, ioaddr + (reg & ~2)); - } else { - writew(val, ioaddr + reg); - } -} - #elif defined(CONFIG_SH_SH4202_MICRODEV) #define SMC_CAN_USE_8BIT 0 @@ -1029,18 +1017,40 @@ static const char * chip_ids[ 16 ] = { #define SMC_SET_MAC_ADDR(lp, addr) \ do { \ - SMC_out16(addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG(lp)); \ - SMC_out16(addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG(lp)); \ - SMC_out16(addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG(lp)); \ + if (SMC_32BIT(lp)) { \ + SMC_outl((addr[0] )|(addr[1] << 8) | \ + (addr[2] << 16)|(addr[3] << 24), \ + ioaddr, ADDR0_REG(lp)); \ + } else { \ + SMC_out16(addr[0]|(addr[1] << 8), ioaddr, \ + ADDR0_REG(lp)); \ + SMC_out16(addr[2]|(addr[3] << 8), ioaddr, \ + ADDR1_REG(lp)); \ + } \ + SMC_out16(addr[4]|(addr[5] << 8), ioaddr, \ + ADDR2_REG(lp)); \ } while (0) #define SMC_SET_MCAST(lp, x) \ do { \ const unsigned char *mt = (x); \ - SMC_out16(mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \ - SMC_out16(mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \ - SMC_out16(mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \ - SMC_out16(mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \ + if (SMC_32BIT(lp)) { \ + SMC_outl((mt[0] ) | (mt[1] << 8) | \ + (mt[2] << 16) | (mt[3] << 24), \ + ioaddr, MCAST_REG1(lp)); \ + SMC_outl((mt[4] ) | (mt[5] << 8) | \ + (mt[6] << 16) | (mt[7] << 24), \ + ioaddr, MCAST_REG3(lp)); \ + } else { \ + SMC_out16(mt[0] | (mt[1] << 8), \ + ioaddr, MCAST_REG1(lp)); \ + SMC_out16(mt[2] | (mt[3] << 8), \ + ioaddr, MCAST_REG2(lp)); \ + SMC_out16(mt[4] | (mt[5] << 8), \ + ioaddr, MCAST_REG3(lp)); \ + SMC_out16(mt[6] | (mt[7] << 8), \ + ioaddr, MCAST_REG4(lp)); \ + } \ } while (0) #define SMC_PUT_PKT_HDR(lp, status, length) \