From patchwork Fri Oct 9 16:53:32 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Drew Richardson X-Patchwork-Id: 54723 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-lb0-f197.google.com (mail-lb0-f197.google.com [209.85.217.197]) by patches.linaro.org (Postfix) with ESMTPS id CF3CC22FFC for ; Fri, 9 Oct 2015 16:54:03 +0000 (UTC) Received: by lbbti1 with SMTP id ti1sf42847845lbb.3 for ; Fri, 09 Oct 2015 09:54:02 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:date:from:to:cc:subject:message-id :references:mime-version:content-type:content-disposition :in-reply-to:user-agent:sender:precedence:list-id:x-original-sender :x-original-authentication-results:mailing-list:list-post:list-help :list-archive:list-unsubscribe; bh=4pOXEjXr/NGQ0vtpV6h1pFuOI45vvcUepwG6ChNCEqA=; b=HbV4pDZInMX4CqGt4YC1W5i/7cmrVCOcre0uwsNHjru7tntYD9VrZFSjquWGudF/zS Ndh5J4NKVdCUFyG5VX8VImNHc8u8jXPEyn9DYKNEto2tftEoJdPAXy3w5f3BRTxyPA0B njEiHepb740lwukFuiUnw4tcqcSal9a7nDZkAlGP3p9z+9w3ureEZ4oN3F9vquHCRV68 SSwQ0SF8Qyew2wLjeunRs9tcw6TleL5pkUznVBqJ/XxbPv/t3PYx8lbmziNIEhQVdqm2 CkRweHhDLvyAW6r9WsJj/SdEHA9sn445ybhhom/fo/N4tEf07BACGLwj4vm4+aNjG0IA iA8w== X-Gm-Message-State: ALoCoQlk3g6wnZ1LPjpHHU1fn2L2WIGUvzhSH2F4ea++antsLNQzwALQO/+aP8Quufsxvtb8Izkf X-Received: by 10.194.156.193 with SMTP id wg1mr2837881wjb.3.1444409642728; Fri, 09 Oct 2015 09:54:02 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.25.208.78 with SMTP id h75ls337473lfg.83.gmail; Fri, 09 Oct 2015 09:54:02 -0700 (PDT) X-Received: by 10.25.90.83 with SMTP id o80mr4513742lfb.47.1444409642535; Fri, 09 Oct 2015 09:54:02 -0700 (PDT) Received: from mail-lb0-f172.google.com (mail-lb0-f172.google.com. [209.85.217.172]) by mx.google.com with ESMTPS id q130si1831630lfq.155.2015.10.09.09.54.02 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Oct 2015 09:54:02 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.172 as permitted sender) client-ip=209.85.217.172; Received: by lbos8 with SMTP id s8so86351190lbo.0 for ; Fri, 09 Oct 2015 09:54:02 -0700 (PDT) X-Received: by 10.25.38.9 with SMTP id m9mr4602300lfm.112.1444409642177; Fri, 09 Oct 2015 09:54:02 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.59.35 with SMTP id w3csp100983lbq; Fri, 9 Oct 2015 09:54:01 -0700 (PDT) X-Received: by 10.107.164.38 with SMTP id n38mr15047634ioe.45.1444409640927; Fri, 09 Oct 2015 09:54:00 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g41si3358523iod.72.2015.10.09.09.54.00; Fri, 09 Oct 2015 09:54:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758227AbbJIQx6 (ORCPT + 30 others); Fri, 9 Oct 2015 12:53:58 -0400 Received: from foss.arm.com ([217.140.101.70]:40425 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752596AbbJIQx4 (ORCPT ); Fri, 9 Oct 2015 12:53:56 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 90C013C; Fri, 9 Oct 2015 09:53:55 -0700 (PDT) Received: from localhost (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 083253F236; Fri, 9 Oct 2015 09:53:55 -0700 (PDT) Date: Fri, 9 Oct 2015 09:53:32 -0700 From: Drew Richardson To: Will Deacon Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Russell King , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Wade Cherry , Pawel Moll Subject: Re: [PATCHv2] arm: perf: Add event descriptions Message-ID: <20151009165330.GA22415@dreric01-gentoo.localdomain> References: <20151007182735.GA18706@dreric01-gentoo.localdomain> <20151009101338.GH26278@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20151009101338.GH26278@arm.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: Drew.Richardson@arm.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.172 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , On Fri, Oct 09, 2015 at 11:13:38AM +0100, Will Deacon wrote: > On Wed, Oct 07, 2015 at 11:28:18AM -0700, Drew Richardson wrote: > > Add additional information about the ARM architected hardware events > > to make counters self describing. This makes the hardware PMUs easier > > to use as perf list contains possible events instead of users having > > to refer to documentation like the ARM TRMs. > > > > Signed-off-by: Drew Richardson > > --- > > arch/arm/kernel/perf_event_v7.c | 96 +++++++++++++++++++++++++++++++++++++++++ > > drivers/perf/arm_pmu.c | 1 + > > 2 files changed, 97 insertions(+) > > > > diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c > > index 126dc679b230..6623bd0d8a1d 100644 > > --- a/arch/arm/kernel/perf_event_v7.c > > +++ b/arch/arm/kernel/perf_event_v7.c > > @@ -547,6 +547,95 @@ static const unsigned scorpion_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] > > [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, > > }; > > > > +static ssize_t armv7_event_sysfs_show(struct device *dev, > > + struct device_attribute *attr, char *page) > > +{ > > + struct perf_pmu_events_attr *pmu_attr; > > + > > + pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr); > > + > > + return sprintf(page, "event=0x%02llx\n", pmu_attr->id); > > +} > > Can we not do this with a couple of macros, stringification of the event > code and PMU_EVENT_ATTR_STRING, therefore avoiding this function entirely? I assumed that doing it this way would be smaller, but using PMU_EVENT_ATTR_STRING is a few hundred bytes smaller, see below. (Please let me know if you'd prefer I send it out in a separate email or even a new thread) > > +#define ARMV7_EVENT_ATTR(name, config) \ > > + PMU_EVENT_ATTR(name, armv7_event_attr_##name, config, \ > > + armv7_event_sysfs_show); > > + > > +ARMV7_EVENT_ATTR(sw_incr, ARMV7_PERFCTR_PMNC_SW_INCR); > > +ARMV7_EVENT_ATTR(l1i_cache_refill, ARMV7_PERFCTR_L1_ICACHE_REFILL); > > +ARMV7_EVENT_ATTR(l1i_tlb_refill, ARMV7_PERFCTR_ITLB_REFILL); > > +ARMV7_EVENT_ATTR(l1d_cache_refill, ARMV7_PERFCTR_L1_DCACHE_REFILL); > > +ARMV7_EVENT_ATTR(l1d_cache, ARMV7_PERFCTR_L1_DCACHE_ACCESS); > > +ARMV7_EVENT_ATTR(l1d_tlb_refill, ARMV7_PERFCTR_DTLB_REFILL); > > +ARMV7_EVENT_ATTR(ld_retired, ARMV7_PERFCTR_MEM_READ); > > +ARMV7_EVENT_ATTR(st_retired, ARMV7_PERFCTR_MEM_WRITE); > > +ARMV7_EVENT_ATTR(inst_retired, ARMV7_PERFCTR_INSTR_EXECUTED); > > +ARMV7_EVENT_ATTR(exc_taken, ARMV7_PERFCTR_EXC_TAKEN); > > +ARMV7_EVENT_ATTR(exc_return, ARMV7_PERFCTR_EXC_EXECUTED); > > +ARMV7_EVENT_ATTR(cid_write_retired, ARMV7_PERFCTR_CID_WRITE); > > +ARMV7_EVENT_ATTR(pc_write_retired, ARMV7_PERFCTR_PC_WRITE); > > +ARMV7_EVENT_ATTR(br_immed_retired, ARMV7_PERFCTR_PC_IMM_BRANCH); > > +ARMV7_EVENT_ATTR(br_return_retired, ARMV7_PERFCTR_PC_PROC_RETURN); > > +ARMV7_EVENT_ATTR(unaligned_ldst_retired, ARMV7_PERFCTR_MEM_UNALIGNED_ACCESS); > > +ARMV7_EVENT_ATTR(br_mis_pred, ARMV7_PERFCTR_PC_BRANCH_MIS_PRED); > > +ARMV7_EVENT_ATTR(cpu_cycles, ARMV7_PERFCTR_CLOCK_CYCLES); > > +ARMV7_EVENT_ATTR(br_pred, ARMV7_PERFCTR_PC_BRANCH_PRED); > > +ARMV7_EVENT_ATTR(mem_access, ARMV7_PERFCTR_MEM_ACCESS); > > +ARMV7_EVENT_ATTR(l1i_cache, ARMV7_PERFCTR_L1_ICACHE_ACCESS); > > +ARMV7_EVENT_ATTR(l1d_cache_wb, ARMV7_PERFCTR_L1_DCACHE_WB); > > +ARMV7_EVENT_ATTR(l2d_cache, ARMV7_PERFCTR_L2_CACHE_ACCESS); > > +ARMV7_EVENT_ATTR(l2d_cache_refill, ARMV7_PERFCTR_L2_CACHE_REFILL); > > +ARMV7_EVENT_ATTR(l2d_cache_wb, ARMV7_PERFCTR_L2_CACHE_WB); > > +ARMV7_EVENT_ATTR(bus_access, ARMV7_PERFCTR_BUS_ACCESS); > > +ARMV7_EVENT_ATTR(memory_error, ARMV7_PERFCTR_MEM_ERROR); > > +ARMV7_EVENT_ATTR(inst_spec, ARMV7_PERFCTR_INSTR_SPEC); > > +ARMV7_EVENT_ATTR(ttbr_write_retired, ARMV7_PERFCTR_TTBR_WRITE); > > +ARMV7_EVENT_ATTR(bus_cycles, ARMV7_PERFCTR_BUS_CYCLES); > > + > > +static struct attribute *armv7_pmuv2_event_attrs[] = { > > + &armv7_event_attr_sw_incr.attr.attr, > > + &armv7_event_attr_l1i_cache_refill.attr.attr, > > + &armv7_event_attr_l1i_tlb_refill.attr.attr, > > + &armv7_event_attr_l1d_cache_refill.attr.attr, > > + &armv7_event_attr_l1d_cache.attr.attr, > > + &armv7_event_attr_l1d_tlb_refill.attr.attr, > > + &armv7_event_attr_ld_retired.attr.attr, > > + &armv7_event_attr_st_retired.attr.attr, > > + &armv7_event_attr_inst_retired.attr.attr, > > + &armv7_event_attr_exc_taken.attr.attr, > > + &armv7_event_attr_exc_return.attr.attr, > > + &armv7_event_attr_cid_write_retired.attr.attr, > > + &armv7_event_attr_pc_write_retired.attr.attr, > > + &armv7_event_attr_br_immed_retired.attr.attr, > > + &armv7_event_attr_br_return_retired.attr.attr, > > + &armv7_event_attr_unaligned_ldst_retired.attr.attr, > > + &armv7_event_attr_br_mis_pred.attr.attr, > > + &armv7_event_attr_cpu_cycles.attr.attr, > > + &armv7_event_attr_br_pred.attr.attr, > > + &armv7_event_attr_mem_access.attr.attr, > > + &armv7_event_attr_l1i_cache.attr.attr, > > + &armv7_event_attr_l1d_cache_wb.attr.attr, > > + &armv7_event_attr_l2d_cache.attr.attr, > > + &armv7_event_attr_l2d_cache_refill.attr.attr, > > + &armv7_event_attr_l2d_cache_wb.attr.attr, > > + &armv7_event_attr_bus_access.attr.attr, > > + &armv7_event_attr_memory_error.attr.attr, > > + &armv7_event_attr_inst_spec.attr.attr, > > + &armv7_event_attr_ttbr_write_retired.attr.attr, > > + &armv7_event_attr_bus_cycles.attr.attr, > > + NULL > > +}; > > + > > +static struct attribute_group armv7_pmuv2_events_attr_group = { > > + .name = "events", > > + .attrs = armv7_pmuv2_event_attrs, > > +}; > > + > > +static const struct attribute_group *armv7_pmuv2_attr_groups[] = { > > + &armv7_pmuv2_events_attr_group, > > + NULL > > +}; > > + > > /* > > * Perf Events' indices > > */ > > @@ -1085,6 +1174,7 @@ static int armv7_a8_pmu_init(struct arm_pmu *cpu_pmu) > > armv7pmu_init(cpu_pmu); > > cpu_pmu->name = "armv7_cortex_a8"; > > cpu_pmu->map_event = armv7_a8_map_event; > > + cpu_pmu->pmu.attr_groups = armv7_pmuv2_attr_groups; > > return armv7_probe_num_events(cpu_pmu); > > } > > > > @@ -1093,6 +1183,7 @@ static int armv7_a9_pmu_init(struct arm_pmu *cpu_pmu) > > armv7pmu_init(cpu_pmu); > > cpu_pmu->name = "armv7_cortex_a9"; > > cpu_pmu->map_event = armv7_a9_map_event; > > + cpu_pmu->pmu.attr_groups = armv7_pmuv2_attr_groups; > > I didn't think these guys supported PMUv2, or is that backwards compatible > with the older event definitions? You're correct. I've added a PMUv1 for the A8, A9 and A5 (the A5 seems to have some PMUv2 events but not all of them and is not documented as having PMUv2 support). > Also, would you be able to do something similar for AArch64 too, please? > (take a look at our for-next/core branch for the latest perf changes). I'll do that and send something out soon. --- Add additional information about the ARM architected hardware events to make counters self describing. This makes the hardware PMUs easier to use as perf list contains possible events instead of users having to refer to documentation like the ARM TRMs. Signed-off-by: Drew Richardson --- arch/arm/kernel/perf_event_v7.c | 119 ++++++++++++++++++++++++++++++++++++++++ drivers/perf/arm_pmu.c | 1 + 2 files changed, 120 insertions(+) diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c index 126dc679b230..3e94e6c22e16 100644 --- a/arch/arm/kernel/perf_event_v7.c +++ b/arch/arm/kernel/perf_event_v7.c @@ -547,6 +547,118 @@ static const unsigned scorpion_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, }; +#define ARMV7_EVENT_ATTR(name, config) \ + PMU_EVENT_ATTR_STRING(name, armv7_event_attr_##name, "event=" #config) + +ARMV7_EVENT_ATTR(sw_incr, 0x00); +ARMV7_EVENT_ATTR(l1i_cache_refill, 0x01); +ARMV7_EVENT_ATTR(l1i_tlb_refill, 0x02); +ARMV7_EVENT_ATTR(l1d_cache_refill, 0x03); +ARMV7_EVENT_ATTR(l1d_cache, 0x04); +ARMV7_EVENT_ATTR(l1d_tlb_refill, 0x05); +ARMV7_EVENT_ATTR(ld_retired, 0x06); +ARMV7_EVENT_ATTR(st_retired, 0x07); +ARMV7_EVENT_ATTR(inst_retired, 0x08); +ARMV7_EVENT_ATTR(exc_taken, 0x09); +ARMV7_EVENT_ATTR(exc_return, 0x0a); +ARMV7_EVENT_ATTR(cid_write_retired, 0x0b); +ARMV7_EVENT_ATTR(pc_write_retired, 0x0c); +ARMV7_EVENT_ATTR(br_immed_retired, 0x0d); +ARMV7_EVENT_ATTR(br_return_retired, 0x0e); +ARMV7_EVENT_ATTR(unaligned_ldst_retired, 0x0f); +ARMV7_EVENT_ATTR(br_mis_pred, 0x10); +ARMV7_EVENT_ATTR(cpu_cycles, 0x11); +ARMV7_EVENT_ATTR(br_pred, 0x12); + +static struct attribute *armv7_pmuv1_event_attrs[] = { + &armv7_event_attr_sw_incr.attr.attr, + &armv7_event_attr_l1i_cache_refill.attr.attr, + &armv7_event_attr_l1i_tlb_refill.attr.attr, + &armv7_event_attr_l1d_cache_refill.attr.attr, + &armv7_event_attr_l1d_cache.attr.attr, + &armv7_event_attr_l1d_tlb_refill.attr.attr, + &armv7_event_attr_ld_retired.attr.attr, + &armv7_event_attr_st_retired.attr.attr, + &armv7_event_attr_inst_retired.attr.attr, + &armv7_event_attr_exc_taken.attr.attr, + &armv7_event_attr_exc_return.attr.attr, + &armv7_event_attr_cid_write_retired.attr.attr, + &armv7_event_attr_pc_write_retired.attr.attr, + &armv7_event_attr_br_immed_retired.attr.attr, + &armv7_event_attr_br_return_retired.attr.attr, + &armv7_event_attr_unaligned_ldst_retired.attr.attr, + &armv7_event_attr_br_mis_pred.attr.attr, + &armv7_event_attr_cpu_cycles.attr.attr, + &armv7_event_attr_br_pred.attr.attr, + NULL +}; + +static struct attribute_group armv7_pmuv1_events_attr_group = { + .name = "events", + .attrs = armv7_pmuv1_event_attrs, +}; + +static const struct attribute_group *armv7_pmuv1_attr_groups[] = { + &armv7_pmuv1_events_attr_group, + NULL +}; + +ARMV7_EVENT_ATTR(mem_access, 0x13); +ARMV7_EVENT_ATTR(l1i_cache, 0x14); +ARMV7_EVENT_ATTR(l1d_cache_wb, 0x15); +ARMV7_EVENT_ATTR(l2d_cache, 0x16); +ARMV7_EVENT_ATTR(l2d_cache_refill, 0x17); +ARMV7_EVENT_ATTR(l2d_cache_wb, 0x18); +ARMV7_EVENT_ATTR(bus_access, 0x19); +ARMV7_EVENT_ATTR(memory_error, 0x1a); +ARMV7_EVENT_ATTR(inst_spec, 0x1b); +ARMV7_EVENT_ATTR(ttbr_write_retired, 0x1c); +ARMV7_EVENT_ATTR(bus_cycles, 0x1d); + +static struct attribute *armv7_pmuv2_event_attrs[] = { + &armv7_event_attr_sw_incr.attr.attr, + &armv7_event_attr_l1i_cache_refill.attr.attr, + &armv7_event_attr_l1i_tlb_refill.attr.attr, + &armv7_event_attr_l1d_cache_refill.attr.attr, + &armv7_event_attr_l1d_cache.attr.attr, + &armv7_event_attr_l1d_tlb_refill.attr.attr, + &armv7_event_attr_ld_retired.attr.attr, + &armv7_event_attr_st_retired.attr.attr, + &armv7_event_attr_inst_retired.attr.attr, + &armv7_event_attr_exc_taken.attr.attr, + &armv7_event_attr_exc_return.attr.attr, + &armv7_event_attr_cid_write_retired.attr.attr, + &armv7_event_attr_pc_write_retired.attr.attr, + &armv7_event_attr_br_immed_retired.attr.attr, + &armv7_event_attr_br_return_retired.attr.attr, + &armv7_event_attr_unaligned_ldst_retired.attr.attr, + &armv7_event_attr_br_mis_pred.attr.attr, + &armv7_event_attr_cpu_cycles.attr.attr, + &armv7_event_attr_br_pred.attr.attr, + &armv7_event_attr_mem_access.attr.attr, + &armv7_event_attr_l1i_cache.attr.attr, + &armv7_event_attr_l1d_cache_wb.attr.attr, + &armv7_event_attr_l2d_cache.attr.attr, + &armv7_event_attr_l2d_cache_refill.attr.attr, + &armv7_event_attr_l2d_cache_wb.attr.attr, + &armv7_event_attr_bus_access.attr.attr, + &armv7_event_attr_memory_error.attr.attr, + &armv7_event_attr_inst_spec.attr.attr, + &armv7_event_attr_ttbr_write_retired.attr.attr, + &armv7_event_attr_bus_cycles.attr.attr, + NULL +}; + +static struct attribute_group armv7_pmuv2_events_attr_group = { + .name = "events", + .attrs = armv7_pmuv2_event_attrs, +}; + +static const struct attribute_group *armv7_pmuv2_attr_groups[] = { + &armv7_pmuv2_events_attr_group, + NULL +}; + /* * Perf Events' indices */ @@ -1085,6 +1197,7 @@ static int armv7_a8_pmu_init(struct arm_pmu *cpu_pmu) armv7pmu_init(cpu_pmu); cpu_pmu->name = "armv7_cortex_a8"; cpu_pmu->map_event = armv7_a8_map_event; + cpu_pmu->pmu.attr_groups = armv7_pmuv1_attr_groups; return armv7_probe_num_events(cpu_pmu); } @@ -1093,6 +1206,7 @@ static int armv7_a9_pmu_init(struct arm_pmu *cpu_pmu) armv7pmu_init(cpu_pmu); cpu_pmu->name = "armv7_cortex_a9"; cpu_pmu->map_event = armv7_a9_map_event; + cpu_pmu->pmu.attr_groups = armv7_pmuv1_attr_groups; return armv7_probe_num_events(cpu_pmu); } @@ -1101,6 +1215,7 @@ static int armv7_a5_pmu_init(struct arm_pmu *cpu_pmu) armv7pmu_init(cpu_pmu); cpu_pmu->name = "armv7_cortex_a5"; cpu_pmu->map_event = armv7_a5_map_event; + cpu_pmu->pmu.attr_groups = armv7_pmuv1_attr_groups; return armv7_probe_num_events(cpu_pmu); } @@ -1110,6 +1225,7 @@ static int armv7_a15_pmu_init(struct arm_pmu *cpu_pmu) cpu_pmu->name = "armv7_cortex_a15"; cpu_pmu->map_event = armv7_a15_map_event; cpu_pmu->set_event_filter = armv7pmu_set_event_filter; + cpu_pmu->pmu.attr_groups = armv7_pmuv2_attr_groups; return armv7_probe_num_events(cpu_pmu); } @@ -1119,6 +1235,7 @@ static int armv7_a7_pmu_init(struct arm_pmu *cpu_pmu) cpu_pmu->name = "armv7_cortex_a7"; cpu_pmu->map_event = armv7_a7_map_event; cpu_pmu->set_event_filter = armv7pmu_set_event_filter; + cpu_pmu->pmu.attr_groups = armv7_pmuv2_attr_groups; return armv7_probe_num_events(cpu_pmu); } @@ -1128,6 +1245,7 @@ static int armv7_a12_pmu_init(struct arm_pmu *cpu_pmu) cpu_pmu->name = "armv7_cortex_a12"; cpu_pmu->map_event = armv7_a12_map_event; cpu_pmu->set_event_filter = armv7pmu_set_event_filter; + cpu_pmu->pmu.attr_groups = armv7_pmuv2_attr_groups; return armv7_probe_num_events(cpu_pmu); } @@ -1135,6 +1253,7 @@ static int armv7_a17_pmu_init(struct arm_pmu *cpu_pmu) { int ret = armv7_a12_pmu_init(cpu_pmu); cpu_pmu->name = "armv7_cortex_a17"; + cpu_pmu->pmu.attr_groups = armv7_pmuv2_attr_groups; return ret; } diff --git a/drivers/perf/arm_pmu.c b/drivers/perf/arm_pmu.c index 2365a32a595e..e933d2dd71c0 100644 --- a/drivers/perf/arm_pmu.c +++ b/drivers/perf/arm_pmu.c @@ -548,6 +548,7 @@ static void armpmu_init(struct arm_pmu *armpmu) .stop = armpmu_stop, .read = armpmu_read, .filter_match = armpmu_filter_match, + .attr_groups = armpmu->pmu.attr_groups, }; }