From patchwork Tue Apr 1 17:29:39 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Catalin Marinas X-Patchwork-Id: 27559 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-pd0-f197.google.com (mail-pd0-f197.google.com [209.85.192.197]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id E0DC520341 for ; Tue, 1 Apr 2014 17:30:28 +0000 (UTC) Received: by mail-pd0-f197.google.com with SMTP id fp1sf25212901pdb.8 for ; Tue, 01 Apr 2014 10:30:28 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:date:from:to:cc:subject:message-id :references:mime-version:in-reply-to:user-agent:sender:precedence :list-id:x-original-sender:x-original-authentication-results :mailing-list:list-post:list-help:list-archive:list-unsubscribe :content-type:content-disposition; bh=GRTeK1sNAkCnHYHKWnGHBSHj4tWPyoRcsXUmWBW5e4Q=; b=Bj357HonBXQaiDHktpqsU5pzTEQzUbc4rGxFkP/UG8RbRAvO5stCHYWQNIHcj3DjWr PfHEViaZgJ8aK8I1QBJpRtProLlzBHySyaKgBhmSy1kF+tITpqFWesq0yO2dBNI+VUM3 MQn+Whi6ioeySrd9i6HQA1ctH6OBbpROwKH56gSOvAvilk1JS5Tkv5S1eYzEcwLPveAB 2ZAolhA2kuU11Oz/kwkhTSDnJpcs/tLovACwzSDM2cjALL0HJCg7TYte7xbYWIC53lvV +vBiBrubvX5iKvLiUIJB9aT6yxKCYCDKMwZUoBzAKfp+H96oBietnj1RRobvlQjFr3dB mYhw== X-Gm-Message-State: ALoCoQn8gtO+UDDpVXWTjBalDgpuFVaAgbP9VvEURFBexC0hyfzj417CKQumlwuwAGnCidELkVBy X-Received: by 10.66.66.196 with SMTP id h4mr13406376pat.22.1396373428213; Tue, 01 Apr 2014 10:30:28 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.47.45 with SMTP id l42ls70856qga.50.gmail; Tue, 01 Apr 2014 10:30:28 -0700 (PDT) X-Received: by 10.52.173.165 with SMTP id bl5mr24581901vdc.13.1396373428099; Tue, 01 Apr 2014 10:30:28 -0700 (PDT) Received: from mail-vc0-f171.google.com (mail-vc0-f171.google.com [209.85.220.171]) by mx.google.com with ESMTPS id kj3si3778632vdb.213.2014.04.01.10.30.28 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 01 Apr 2014 10:30:28 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.220.171 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.220.171; Received: by mail-vc0-f171.google.com with SMTP id lg15so10461710vcb.30 for ; Tue, 01 Apr 2014 10:30:28 -0700 (PDT) X-Received: by 10.52.123.97 with SMTP id lz1mr120738vdb.73.1396373427999; Tue, 01 Apr 2014 10:30:27 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.220.12.8 with SMTP id v8csp256136vcv; Tue, 1 Apr 2014 10:30:27 -0700 (PDT) X-Received: by 10.67.23.135 with SMTP id ia7mr32508492pad.5.1396373427176; Tue, 01 Apr 2014 10:30:27 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id xi5si6705953pab.406.2014.04.01.10.30.26; Tue, 01 Apr 2014 10:30:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751592AbaDARaO (ORCPT + 27 others); Tue, 1 Apr 2014 13:30:14 -0400 Received: from fw-tnat.austin.arm.com ([217.140.110.23]:59282 "EHLO collaborate-mta1.arm.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751255AbaDARaM (ORCPT ); Tue, 1 Apr 2014 13:30:12 -0400 Received: from arm.com (e102109-lin.cambridge.arm.com [10.1.203.182]) by collaborate-mta1.arm.com (Postfix) with ESMTPS id 5A3DF13F796; Tue, 1 Apr 2014 12:30:01 -0500 (CDT) Date: Tue, 1 Apr 2014 18:29:39 +0100 From: Catalin Marinas To: "Jon Medhurst (Tixy)" Cc: "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Liviu Dudau Subject: Re: Bug(?) in patch "arm64: Implement coherent DMA API based on swiotlb" (was Re: [GIT PULL] arm64 patches for 3.15) Message-ID: <20140401172939.GG20061@arm.com> References: <20140331175230.GA7480@arm.com> <1396368657.3681.17.camel@linaro1.home> MIME-Version: 1.0 In-Reply-To: <1396368657.3681.17.camel@linaro1.home> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: catalin.marinas@arm.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.171 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Content-Disposition: inline On Tue, Apr 01, 2014 at 05:10:57PM +0100, Jon Medhurst (Tixy) wrote: > On Mon, 2014-03-31 at 18:52 +0100, Catalin Marinas wrote: > > The following changes since commit cfbf8d4857c26a8a307fb7cd258074c9dcd8c691: > > > > Linux 3.14-rc4 (2014-02-23 17:40:03 -0800) > > > > are available in the git repository at: > > > > git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux tags/arm64-upstream > > > > for you to fetch changes up to 196adf2f3015eacac0567278ba538e3ffdd16d0e: > > > > arm64: Remove pgprot_dmacoherent() (2014-03-24 10:35:35 +0000) > > I may have spotted a bug in commit 7363590d2c46 (arm64: Implement > coherent DMA API based on swiotlb), see my inline comment below... > > [...] > > diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S > > index 1ea9f26..97fcef5 100644 > > --- a/arch/arm64/mm/cache.S > > +++ b/arch/arm64/mm/cache.S > > @@ -166,3 +166,81 @@ ENTRY(__flush_dcache_area) > > dsb sy > > ret > > ENDPROC(__flush_dcache_area) > > + > > +/* > > + * __dma_inv_range(start, end) > > + * - start - virtual start address of region > > + * - end - virtual end address of region > > + */ > > +__dma_inv_range: > > + dcache_line_size x2, x3 > > + sub x3, x2, #1 > > + bic x0, x0, x3 > > + bic x1, x1, x3 > > Why is the 'end' value in x1 above rounded down to be cache aligned? > This means the cache invalidate won't include the cache line containing > the final bytes of the region, unless it happened to already be cache > line aligned. This looks especially suspect as the other two cache > operations added in the same patch (below) don't do that. Cache invalidation is destructive, so we want to make sure that it doesn't affect anything beyond x1. But you are right, if either end of the buffer is not cache line aligned it can get it wrong. The fix is to use clean+invalidate on the unaligned ends: diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S index c46f48b33c14..6a26bf1965d3 100644 --- a/arch/arm64/mm/cache.S +++ b/arch/arm64/mm/cache.S @@ -175,10 +175,17 @@ ENDPROC(__flush_dcache_area) __dma_inv_range: dcache_line_size x2, x3 sub x3, x2, #1 - bic x0, x0, x3 + tst x1, x3 // end cache line aligned? bic x1, x1, x3 -1: dc ivac, x0 // invalidate D / U line - add x0, x0, x2 + b.eq 1f + dc civac, x1 // clean & invalidate D / U line +1: tst x0, x3 // start cache line aligned? + bic x0, x0, x3 + b.eq 2f + dc civac, x0 // clean & invalidate D / U line + b 3f +2: dc ivac, x0 // invalidate D / U line +3: add x0, x0, x2 cmp x0, x1 b.lo 1b dsb sy