From patchwork Thu Jul 7 15:13:32 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 2569 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 4545B2412F for ; Thu, 7 Jul 2011 15:07:10 +0000 (UTC) Received: from mail-qy0-f173.google.com (mail-qy0-f173.google.com [209.85.216.173]) by fiordland.canonical.com (Postfix) with ESMTP id EC48DA18461 for ; Thu, 7 Jul 2011 15:07:09 +0000 (UTC) Received: by qyk10 with SMTP id 10so3233554qyk.11 for ; Thu, 07 Jul 2011 08:07:09 -0700 (PDT) Received: by 10.229.62.194 with SMTP id y2mr713109qch.4.1310051229324; Thu, 07 Jul 2011 08:07:09 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.229.48.135 with SMTP id r7cs110360qcf; Thu, 7 Jul 2011 08:07:08 -0700 (PDT) Received: by 10.52.100.40 with SMTP id ev8mr1203861vdb.156.1310051227676; Thu, 07 Jul 2011 08:07:07 -0700 (PDT) Received: from TX2EHSOBE007.bigfish.com (tx2ehsobe004.messaging.microsoft.com [65.55.88.14]) by mx.google.com with ESMTPS id p9si11367992vdg.62.2011.07.07.08.07.07 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 07 Jul 2011 08:07:07 -0700 (PDT) Received-SPF: neutral (google.com: 65.55.88.14 is neither permitted nor denied by best guess record for domain of r65073@freescale.com) client-ip=65.55.88.14; Authentication-Results: mx.google.com; spf=neutral (google.com: 65.55.88.14 is neither permitted nor denied by best guess record for domain of r65073@freescale.com) smtp.mail=r65073@freescale.com Received: from mail58-tx2-R.bigfish.com (10.9.14.251) by TX2EHSOBE007.bigfish.com (10.9.40.27) with Microsoft SMTP Server id 14.1.225.22; Thu, 7 Jul 2011 15:07:06 +0000 Received: from mail58-tx2 (localhost.localdomain [127.0.0.1]) by mail58-tx2-R.bigfish.com (Postfix) with ESMTP id 98C34C68520; Thu, 7 Jul 2011 15:07:06 +0000 (UTC) X-SpamScore: -9 X-BigFish: VS-9(zz1432N98dKzz1202hzz8275dhz2dh2a8h668h839h944h61h) X-Spam-TCS-SCL: 0:0 X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPVD:NLI; H:mail.freescale.net; RD:none; EFVD:NLI Received: from mail58-tx2 (localhost.localdomain [127.0.0.1]) by mail58-tx2 (MessageSwitch) id 131005122683232_11954; Thu, 7 Jul 2011 15:07:06 +0000 (UTC) Received: from TX2EHSMHS018.bigfish.com (unknown [10.9.14.249]) by mail58-tx2.bigfish.com (Postfix) with ESMTP id EA2CB500059; Thu, 7 Jul 2011 15:07:05 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by TX2EHSMHS018.bigfish.com (10.9.99.118) with Microsoft SMTP Server (TLS) id 14.1.225.22; Thu, 7 Jul 2011 15:07:04 +0000 Received: from az33smr01.freescale.net (10.64.34.199) by 039-SN1MMR1-001.039d.mgd.msft.net (10.84.1.13) with Microsoft SMTP Server id 14.1.289.8; Thu, 7 Jul 2011 10:07:04 -0500 Received: from S2100-06.ap.freescale.net (S2100-06.ap.freescale.net [10.192.242.125]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id p67F70mM021755; Thu, 7 Jul 2011 10:07:01 -0500 (CDT) Date: Thu, 7 Jul 2011 23:13:32 +0800 From: Shawn Guo To: Sascha Hauer CC: Shawn Guo , , , , , Grant Likely Subject: Re: [PATCH v3 2/3] ARM: mxc: use ARCH_NR_GPIOS to define gpio number Message-ID: <20110707151331.GB12722@S2100-06.ap.freescale.net> References: <1309970263-13239-1-git-send-email-shawn.guo@linaro.org> <1309970263-13239-3-git-send-email-shawn.guo@linaro.org> <20110707074755.GX6069@pengutronix.de> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20110707074755.GX6069@pengutronix.de> User-Agent: Mutt/1.5.21 (2010-09-15) X-OriginatorOrg: freescale.com On Thu, Jul 07, 2011 at 09:47:55AM +0200, Sascha Hauer wrote: > On Thu, Jul 07, 2011 at 12:37:42AM +0800, Shawn Guo wrote: > > The patch removes MXC_GPIO_IRQS and instead uses ARCH_NR_GPIOS to > > define gpio number. This change is need when we change mxc gpio > > driver to be device tree aware. When migrating the driver to device > > tree, pdev->id becomes unusable. It requires driver get gpio range > > from gpio core, which will dynamically allocates number from > > ARCH_NR_GPIOS to 0. > > > > As a bonus point, it removes lines of '#if' and make the code a > > little bit cleaner. The side effect is the waste of number. But > > this is not a point when we go single image. > > I'm not sure whether we really should depend on an externally defined > ARCH_NR_GPIOS. Someone might get the idea to change this to a lower > value. Maybe we should define this ourselves instead. > Good point. We should not depend on the externally defined one. But the reason in my mind is different from yours. Right now, i.mx50 gets 192 and i.mx6 gets 224 gpios. I do not see the point to lower the value (no lower than 224), since we will go single image soon. The thing concerning me is that someday we may have a soc coming out with more than 256 gpios. Then we have to override ARCH_NR_GPIOS with our own definition. Please take a look at the updated patch below. If it looks fine to you, I will resend the patch. 8<---- >From b9cc9f9161b6d5ebb57d52200c3673dd78138899 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Wed, 6 Jul 2011 21:11:01 +0800 Subject: [PATCH] ARM: mxc: use ARCH_NR_GPIOS to define gpio number The patch removes MXC_GPIO_IRQS and instead uses ARCH_NR_GPIOS to define gpio number. This change is need when we change mxc gpio driver to be device tree aware. When migrating the driver to device tree, pdev->id becomes unusable. It requires driver get gpio range from gpio core, which will dynamically allocates number from ARCH_NR_GPIOS to 0. As a bonus point, it removes lines of '#if' and make the code a little bit cleaner. It also cleans a couple of unnecessary headers in mach/gpio.h. Signed-off-by: Shawn Guo Cc: Sascha Hauer Cc: Grant Likely --- arch/arm/plat-mxc/include/mach/gpio.h | 9 ++++++--- arch/arm/plat-mxc/include/mach/irqs.h | 21 +++------------------ 2 files changed, 9 insertions(+), 21 deletions(-) diff --git a/arch/arm/plat-mxc/include/mach/gpio.h b/arch/arm/plat-mxc/include/mach/gpio.h index 31c820c..f3b26f7 100644 --- a/arch/arm/plat-mxc/include/mach/gpio.h +++ b/arch/arm/plat-mxc/include/mach/gpio.h @@ -19,10 +19,13 @@ #ifndef __ASM_ARCH_MXC_GPIO_H__ #define __ASM_ARCH_MXC_GPIO_H__ -#include -#include -#include +/* + * Define our own ARCH_NR_GPIOS here to override the one + * externally defined in asm-generic/gpio.h + */ +#define ARCH_NR_GPIOS 224 +#include /* There's a off-by-one betweem the gpio bank number and the gpiochip */ /* range e.g. GPIO_1_5 is gpio 5 under linux */ diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h index 35c89bc..62228f1 100644 --- a/arch/arm/plat-mxc/include/mach/irqs.h +++ b/arch/arm/plat-mxc/include/mach/irqs.h @@ -11,6 +11,8 @@ #ifndef __ASM_ARCH_MXC_IRQS_H__ #define __ASM_ARCH_MXC_IRQS_H__ +#include + /* * SoCs with TZIC interrupt controller have 128 IRQs, those with AVIC have 64 */ @@ -22,30 +24,13 @@ #define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS -/* these are ordered by size to support multi-SoC kernels */ -#if defined CONFIG_SOC_IMX53 -#define MXC_GPIO_IRQS (32 * 7) -#elif defined CONFIG_ARCH_MX2 -#define MXC_GPIO_IRQS (32 * 6) -#elif defined CONFIG_SOC_IMX50 -#define MXC_GPIO_IRQS (32 * 6) -#elif defined CONFIG_ARCH_MX1 -#define MXC_GPIO_IRQS (32 * 4) -#elif defined CONFIG_ARCH_MX25 -#define MXC_GPIO_IRQS (32 * 4) -#elif defined CONFIG_SOC_IMX51 -#define MXC_GPIO_IRQS (32 * 4) -#elif defined CONFIG_ARCH_MX3 -#define MXC_GPIO_IRQS (32 * 3) -#endif - /* * The next 16 interrupts are for board specific purposes. Since * the kernel can only run on one machine at a time, we can re-use * these. If you need more, increase MXC_BOARD_IRQS, but keep it * within sensible limits. */ -#define MXC_BOARD_IRQ_START (MXC_INTERNAL_IRQS + MXC_GPIO_IRQS) +#define MXC_BOARD_IRQ_START (MXC_INTERNAL_IRQS + ARCH_NR_GPIOS) #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 #define MXC_BOARD_IRQS 80