From patchwork Mon Oct 21 16:21:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 177117 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp3636431ill; Mon, 21 Oct 2019 09:26:34 -0700 (PDT) X-Google-Smtp-Source: APXvYqwlBtVM2vpXZ15HFt0ePZbqNEoMigCFzlPK9sDUAatO5FRdoxKUjvi1kXjUijYdk8c8x/ZD X-Received: by 2002:a05:6402:1a55:: with SMTP id bf21mr3373695edb.61.1571675194052; Mon, 21 Oct 2019 09:26:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571675194; cv=none; d=google.com; s=arc-20160816; b=I42MRvdoUfI30iJgK50+N7PNnZOIV/+QNIj0kFI/0vK5NTGH44sw+oX5wYEKefSl9F /VG1cUoEHSe/IcgGkwrOhui4BYJkegs84Uq7XUROT5iNhP+8j8Y0zB4XJVSedWyWkW4v BlRFjH4X7L8dcbhSP3XQUYCI0d8V8GgMhcwxfZN8JwuVa4V60klVC9kYe2tG00Lfe+fP WIwkiawOJ6iyuIV2SrAzdKBSVOrARDFbg6DuHPHybm1NshfatCR32oMl7SMFhX12GRCi peaJduCFR9CuhMSOyv0hNYA2FKagghzNB/idmBVIIw//Vx5QaADgx0nMaiO+36tt/Rfz 39DA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=rUCy0US1o8lGrV47tXlj9moDifDnqM31y9Roq/EJg2o=; b=nG287LOXsHZpiikKQFgZ8cuZ33ONhcRSwZi0A9DXhFN5oxJ4c7Wt42FBaMNZx7F2ER lJuW/FuFShDu+xtg6jeHwUigTTzYKsIg5fT2QYZljLQ01rofq0+WNSaWVVvwTJvcQsqM kePunGYUGFKTX+dtglEesGLUoMa2sXc7d703E6xkfdy9vayzaq3JfQ6rIN4yWcEEEW3C ZoojBoLLwAYz7/FkOos9/hUXheyyLPQ+rWOkFaVCKTDdupUixCwjkWS3a/n1M0jcMy3d 9AS3WNwYdcwGgGkKCLNIjxLp+2CIX6pGHot0MVnXNQWjZKIe6EIf+UWB7B+rzaivkC+7 vRhg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p9si9474463edx.273.2019.10.21.09.26.33; Mon, 21 Oct 2019 09:26:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729062AbfJUQZ3 (ORCPT + 26 others); Mon, 21 Oct 2019 12:25:29 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:33124 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726276AbfJUQZ2 (ORCPT ); Mon, 21 Oct 2019 12:25:28 -0400 Received: from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id EBC81B6BD90BF05A997D; Tue, 22 Oct 2019 00:25:24 +0800 (CST) Received: from localhost.localdomain (10.69.192.58) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.439.0; Tue, 22 Oct 2019 00:25:17 +0800 From: John Garry To: , CC: , , , Xiang Chen , "John Garry" Subject: [PATCH 02/18] scsi: hisi_sas: Set the BIST init value before enabling BIST Date: Tue, 22 Oct 2019 00:21:59 +0800 Message-ID: <1571674935-108326-3-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1571674935-108326-1-git-send-email-john.garry@huawei.com> References: <1571674935-108326-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.58] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiang Chen If set the BIST init value after enabling BIST, there may be still some few error bits. According to the process, need to set the BIST init value before enabling BIST. Fixes: 97b151e75861 ("scsi: hisi_sas: Add BIST support for phy loopback") Signed-off-by: Xiang Chen Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index cb8d087762db..cc594937fa8d 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -3022,11 +3022,6 @@ static int debugfs_set_bist_v3_hw(struct hisi_hba *hisi_hba, bool enable) hisi_sas_phy_write32(hisi_hba, phy_id, SAS_PHY_BIST_CTRL, reg_val); - mdelay(100); - reg_val |= (CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK); - hisi_sas_phy_write32(hisi_hba, phy_id, - SAS_PHY_BIST_CTRL, reg_val); - /* set the bist init value */ hisi_sas_phy_write32(hisi_hba, phy_id, SAS_PHY_BIST_CODE, @@ -3035,6 +3030,11 @@ static int debugfs_set_bist_v3_hw(struct hisi_hba *hisi_hba, bool enable) SAS_PHY_BIST_CODE1, SAS_PHY_BIST_CODE1_INIT); + mdelay(100); + reg_val |= (CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK); + hisi_sas_phy_write32(hisi_hba, phy_id, + SAS_PHY_BIST_CTRL, reg_val); + /* clear error bit */ mdelay(100); hisi_sas_phy_read32(hisi_hba, phy_id, SAS_BIST_ERR_CNT);