From patchwork Tue Jun 18 10:02:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Erwan Le Ray X-Patchwork-Id: 167130 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp4002235ilk; Tue, 18 Jun 2019 03:03:13 -0700 (PDT) X-Google-Smtp-Source: APXvYqxK/bTVyBJjs4vzAomI1VQKJwZjlo6xsMPFDNhgg31yggeSHoWfnBNkoh67ZzPTDwy5fjaV X-Received: by 2002:a65:5347:: with SMTP id w7mr1895980pgr.375.1560852193279; Tue, 18 Jun 2019 03:03:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560852193; cv=none; d=google.com; s=arc-20160816; b=K1xzmTWvtnC4Ega7OFLFR2PDcV7aMMdY7dDgK8KOQzF+NnWNWK6FAzQm6sUX9vXBt8 f9esPnwAF/avtoPnk4gA6CvbAAD89l3XGVl6/qBN2K0/8U7EDYzH4YZf8KKHIkDvcSlf gvtpriQooX5s/0LZ8e5MxxIcBj4yq3Rfg0+phN3tZ+lk4bcp13YY/CCU8ZqbpJ3K4huN Pnd0WQ9HNKXNvav4ehwj2bDhjQP0u3fVzOLaDJ62JzyG3P1mxPlQIPqxy5wNDROeqj34 0C7UVD3T0jWHQU40H/JGWf3qF7vvg/3vrtOpYpzmC5bfDA5zmkMVwKe8RedA/WcmCueS nodw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=Z42l/er6av5f1snpxyojUBAWUdIxDz7JA7iDhJQHpuU=; b=VP6rG3H5M9UWai7rJQRRi84F80WBMUKAF1cOtdokPzmmQpmgiUl3o6AbxZJOHq4sQr wBS95DsWYIYroyGvv8wRHbHiUIKqr6526nDCFAwIvWzGFuKaxs1Fnrsaz8G4kalWJ6Ci wlqeuUKIcWpgMLpr7Kl8OB81lIM2AGWX3umjssouwGqdDO8IpsLbxmH5uI51elhSx+pX N8xg9fAJSh0jm6juyd60tC0bDQZjFS/+cHXvMhKaun9BGMWYJT5YZEAk7r5mBeGpNyto lIHFIzBe/zc55vtR8Hc+NQwXLOt3Bg4HZ52s3KpZDbtpv+KT2FjsDXk5LSzesTDVpBeH w4Rg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@st.com header.s=STMicroelectronics header.b=eUVMYnKo; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y62si12861616pfy.244.2019.06.18.03.03.12; Tue, 18 Jun 2019 03:03:13 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@st.com header.s=STMicroelectronics header.b=eUVMYnKo; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729315AbfFRKDL (ORCPT + 29 others); Tue, 18 Jun 2019 06:03:11 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:50850 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726023AbfFRKDI (ORCPT ); Tue, 18 Jun 2019 06:03:08 -0400 Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x5IA1k9d030829; Tue, 18 Jun 2019 12:02:43 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=STMicroelectronics; bh=Z42l/er6av5f1snpxyojUBAWUdIxDz7JA7iDhJQHpuU=; b=eUVMYnKoUvAm+F86HXEetOou9H/SsPwQcTj1OD9rJ6Z65p176NxdFstUI/E5T3yJYVcY VEPVkRDix8zqfuR3UdNA3cR09jyOcs2ZR5e/M++sE+car9/c6z+ZTBKq72S7LmmZQDj9 pW9Pjx45EDcmya/baNQ8peZc0CfDCv+N3GH5qjTCMZiQnSk0RcYn5ma8885BU81wmzuT r+iRX5mmBHNpS7a2WRSOX1z5/xzs+44WPLFKjFFTEouT63Nb+vVgfCM7f6lcK4XA9kJc PhbwntXbx9WnZE3YAIL3kcPA2d+2gl4Cz3mmpQoMqx+7/WW3/UW7pL57S1HFzVY8tuzk 0w== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2t68n3nv0a-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 18 Jun 2019 12:02:43 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id A81223A; Tue, 18 Jun 2019 10:02:42 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas22.st.com [10.75.90.92]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 7F25F25DD; Tue, 18 Jun 2019 10:02:42 +0000 (GMT) Received: from SAFEX1HUBCAS23.st.com (10.75.90.47) by Safex1hubcas22.st.com (10.75.90.92) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 18 Jun 2019 12:02:42 +0200 Received: from localhost (10.201.23.31) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 18 Jun 2019 12:02:42 +0200 From: Erwan Le Ray To: Greg Kroah-Hartman , Jiri Slaby , Maxime Coquelin , "Alexandre Torgue" CC: , , , , "Erwan Le Ray" , Fabrice Gasnier Subject: [PATCH 4/5] serial: stm32: add support of RX FIFO threshold Date: Tue, 18 Jun 2019 12:02:25 +0200 Message-ID: <1560852146-3393-5-git-send-email-erwan.leray@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1560852146-3393-1-git-send-email-erwan.leray@st.com> References: <1560852146-3393-1-git-send-email-erwan.leray@st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.23.31] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-18_05:, , signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Adds the support of RX FIFO threshold in order to improve the RX FIFO management. This is done by enabling fifo threshold interrupt, instead of relying on rx empty/fifo not full irq. That basically generates one irq/char currently. With this patch: - RXCFG is set to half fifo size (e.g. 16/2 = 8 data for a 16 data depth FIFO) - irq rate may be reduced by up to 1/RXCFG, e.g. 1 over 8 with current RXCFG setting. - Receiver timeout is used to gather chars when FIFO threshold isn't reached. Signed-off-by: Erwan Le Ray -- 1.9.1 diff --git a/drivers/tty/serial/stm32-usart.c b/drivers/tty/serial/stm32-usart.c index 397d86d..4083145 100644 --- a/drivers/tty/serial/stm32-usart.c +++ b/drivers/tty/serial/stm32-usart.c @@ -550,6 +550,9 @@ static void stm32_throttle(struct uart_port *port) spin_lock_irqsave(&port->lock, flags); stm32_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); + if (stm32_port->cr3_irq) + stm32_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); + spin_unlock_irqrestore(&port->lock, flags); } @@ -562,6 +565,9 @@ static void stm32_unthrottle(struct uart_port *port) spin_lock_irqsave(&port->lock, flags); stm32_set_bits(port, ofs->cr1, stm32_port->cr1_irq); + if (stm32_port->cr3_irq) + stm32_set_bits(port, ofs->cr3, stm32_port->cr3_irq); + spin_unlock_irqrestore(&port->lock, flags); } @@ -572,6 +578,9 @@ static void stm32_stop_rx(struct uart_port *port) struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; stm32_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); + if (stm32_port->cr3_irq) + stm32_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); + } /* Handle breaks - ignored by us */ @@ -600,8 +609,9 @@ static int stm32_startup(struct uart_port *port) if (stm32_port->fifoen) { val = readl_relaxed(port->membase + ofs->cr3); - val &= ~USART_CR3_TXFTCFG_MASK; + val &= ~(USART_CR3_TXFTCFG_MASK | USART_CR3_RXFTCFG_MASK); val |= USART_CR3_TXFTCFG_HALF << USART_CR3_TXFTCFG_SHIFT; + val |= USART_CR3_RXFTCFG_HALF << USART_CR3_RXFTCFG_SHIFT; writel_relaxed(val, port->membase + ofs->cr3); } @@ -693,7 +703,7 @@ static void stm32_set_termios(struct uart_port *port, struct ktermios *termios, cr1 |= USART_CR1_FIFOEN; cr2 = 0; cr3 = readl_relaxed(port->membase + ofs->cr3); - cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTCFG | USART_CR3_RXFTIE + cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTCFG_MASK | USART_CR3_RXFTIE | USART_CR3_TXFTCFG_MASK; if (cflag & CSTOPB) @@ -733,8 +743,14 @@ static void stm32_set_termios(struct uart_port *port, struct ktermios *termios, stm32_port->cr1_irq = USART_CR1_RTOIE; writel_relaxed(bits, port->membase + ofs->rtor); cr2 |= USART_CR2_RTOEN; + /* Not using dma, enable fifo threshold irq */ + if (!stm32_port->rx_ch) + stm32_port->cr3_irq = USART_CR3_RXFTIE; } + cr1 |= stm32_port->cr1_irq; + cr3 |= stm32_port->cr3_irq; + if (cflag & PARODD) cr1 |= USART_CR1_PS; @@ -976,6 +992,7 @@ static struct stm32_port *stm32_of_get_stm32_port(struct platform_device *pdev) "st,hw-flow-ctrl"); stm32_ports[id].port.line = id; stm32_ports[id].cr1_irq = USART_CR1_RXNEIE; + stm32_ports[id].cr3_irq = 0; stm32_ports[id].last_res = RX_BUF_L; return &stm32_ports[id]; } diff --git a/drivers/tty/serial/stm32-usart.h b/drivers/tty/serial/stm32-usart.h index a598446..a175c10 100644 --- a/drivers/tty/serial/stm32-usart.h +++ b/drivers/tty/serial/stm32-usart.h @@ -210,7 +210,8 @@ struct stm32_usart_info stm32h7_info = { #define USART_CR3_WUFIE BIT(22) /* H7 */ #define USART_CR3_TXFTIE BIT(23) /* H7 */ #define USART_CR3_TCBGTIE BIT(24) /* H7 */ -#define USART_CR3_RXFTCFG GENMASK(27, 25) /* H7 */ +#define USART_CR3_RXFTCFG_MASK GENMASK(27, 25) /* H7 */ +#define USART_CR3_RXFTCFG_SHIFT 25 /* H7 */ #define USART_CR3_RXFTIE BIT(28) /* H7 */ #define USART_CR3_TXFTCFG_MASK GENMASK(31, 29) /* H7 */ #define USART_CR3_TXFTCFG_SHIFT 29 /* H7 */ @@ -218,6 +219,9 @@ struct stm32_usart_info stm32h7_info = { /* TX FIFO threashold set to half of its depth */ #define USART_CR3_TXFTCFG_HALF 0x2 +/* RX FIFO threashold set to half of its depth */ +#define USART_CR3_RXFTCFG_HALF 0x2 + /* USART_GTPR */ #define USART_GTPR_PSC_MASK GENMASK(7, 0) #define USART_GTPR_GT_MASK GENMASK(15, 8) @@ -263,6 +267,7 @@ struct stm32_port { dma_addr_t tx_dma_buf; /* dma tx buffer bus address */ unsigned char *tx_buf; /* dma tx buffer cpu address */ u32 cr1_irq; /* USART_CR1_RXNEIE or RTOIE */ + u32 cr3_irq; /* USART_CR3_RXFTIE */ int last_res; bool tx_dma_busy; /* dma tx busy */ bool hw_flow_control;